參數(shù)資料
型號(hào)： MAX5866ETM+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 6/26頁(yè)
文件大?。?/td> 0K
描述： IC ANLG FRONT END 60MSPS 48-TQFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 10
通道數(shù)： 4
功率（瓦特）： 2.10W
電壓 - 電源，模擬： 2.7 V ~ 3.3 V
電壓 - 電源，數(shù)字： 2.7 V ~ 3.3 V
封裝/外殼： 48-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 48-TQFN-EP（7x7）
包裝： 帶卷 (TR)
MAX5866
Dual 8-Bit ADC
The ADC uses a seven-stage, fully differential,
pipelined architecture that allows for high-speed con-
version while minimizing power consumption. Samples
taken at the inputs move progressively through the
pipeline stages every half clock cycle. Including the
delay through the output latch, the total clock-cycle
latency is 5 clock cycles for channel IA and 5.5 clock
cycles for channel QA. The ADC’s full-scale analog
input range is ±VREF with a common-mode input range
of VDD / 2 ±0.2V. VREF is the difference between VREFP
and VREFN. See the Reference Configurations section
for details.
Input Track-and-Hold (T/H) Circuits
Figure 1 displays a simplified functional diagram of the
ADC’s input T/H circuitry. In track mode, switches S1,
S2a, S2b, S4a, S4b, S5a, and S5b are closed. The fully
differential circuits sample the input signals onto the
two capacitors (C2a and C2b) through switches S4a
and S4b. S2a and S2b set the common mode for the
amplifier input, and open simultaneously with S1, sam-
pling the input waveform. Switches S4a, S4b, S5a, and
S5b are then opened before switches S3a and S3b
connect capacitors C1a and C1b to the output of the
amplifier and switch S4c is closed. The resulting differ-
ential voltages are held on capacitors C2a and C2b.
The amplifiers charge capacitors C1a and C1b to the
same values originally held on C2a and C2b. These val-
ues are then presented to the first-stage quantizers and
isolate the pipelines from the fast-changing inputs. The
wide input bandwidth T/H amplifiers allow the ADC to
track and sample/hold analog inputs of high frequen-
cies (> Nyquist). Both ADC inputs (IA+, QA+, IA-, and
QA-) can be driven either differentially or single ended.
Match the impedance of IA+ and IA-, as well as QA+
and QA-, and set the common-mode voltage to mid-
supply (VDD / 2) for optimum performance.
ADC Digital Output Data (DA0–DA7)
DA0–DA7 are the ADCs’ digital logic outputs. The logic
level is set by OVDD from +2.7V to VDD. The digital out-
put coding is offset binary (Table 1, Figure 2). The
capacitive load on digital outputs DA0–DA7 should be
kept as low as possible (<15pF) to avoid large digital
currents feeding back into the analog portion of the
MAX5866 and degrading its dynamic performance.
Buffers on the digital outputs isolate them from heavy
capacitive loads. Adding 100 resistors in series with
the digital outputs close to the MAX5866 helps improve
ADC performance. Refer to the MAX5865 EV kit
schematic for an example of the digital outputs driving
a digital buffer through 100 series resistors.
Ultra-Low-Power, High-Dynamic-
Performance, 60Msps Analog Front End
14
______________________________________________________________________________________
Table 1. Output Codes vs. Input Voltage
DIFFERENTIAL
INPUT VOLTAGE
DIFFERENTIAL INPUT
(LSB)
OFFSET BINARY
(DA7–DA0)
OUTPUT DECIMAL
CODE
127
(+full scale - 1LSB)
1111 1111
255
126
(+full scale - 2LSB)
1111 1110
254
+1
1000 0001
129
0
(bipolar zero)
1000 0000
128
-1
0111 1111
127
-127
(-full scale + 1LSB)
0000 0001
1
-128
(-full scale)
0000 0000
0
VREF
127
128
×
VREF
126
128
×
VREF
1
128
×
VREF
0
128
×
VREF
1
128
×
VREF
127
128
×
VREF
128
×
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