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E
MAX5858A Evaluation Kit
4
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Detailed Description
The MAX5858A EV kit is designed to simplify the evalu-
ation of the MAX5858A 10-bit, dual, 300Msps DAC with
PLL. The board contains all circuitry necessary to eval-
uate the dynamic performance of this high-speed con-
verter, including circuitry to convert the DAC’s differen-
tial output into a single-ended output.
The EV kit provides PC board connector pads for
power supplies AVDDIN, DVDDIN, and PVDDIN. SMA
connectors are included for clock functions CLKIN,
CLKOUT, CLKD, and DAC outputs OUTA and OUTB
connections. The four-layer PC board is a high-speed
design that optimizes the dynamic performance of the
DAC by separating the analog and digital circuitry,
which implements impedance matching for the differ-
ential output signal PC board traces. The PC board
traces have been designed for 50
impedance.
Power Supplies
The MAX5858A EV kit requires separate analog, digital,
and PLL power supplies. Connect a 3V power supply to
the AVDDIN PC board pad to power the analog portion
of the DAC. Connect the second 3V power supply to the
DVDDIN PC board pad to power the digital portion of
the DAC. Connect the third 3V power supply to the PVD-
DIN PC board pad to power the PLL portion of the DAC.
Digital Inputs
The MAX5858A EV kit provides connector J1 for the
two 10-bit input data buses. Data bits DA9 through DA2
of channel A share a dual function for data and control
word. The control word is latched by the
CW
bit (J1-1).
The control word is latched on the falling edge of
CW
.
Refer to the MAX5858A data sheet for a detailed
description of the control and data word functions. The
data word is latched on the rising edge of the CLK out-
put, pin 20 of the MAX5858A.
DAC Output
The MAX5858A EV kit is designed to provide two pairs
of analog outputs. The outputs can be configured for
either differential or single-ended mode of operation. In
differential mode and with transformer-coupled output
and 50
external termination, the MAX5858A delivers a
-2dBm output signal. In single-ended mode, the output
amplitude is 1V
P-P
at both positive and negative DAC
outputs. To configure the MAX5858A for single-ended
output operation, remove jumpers JU6–JU9, and mea-
sure the outputs at the A+, A-, and B+, B- 2-pin head-
ers. To configure the MAX5858A for differential output
operation, install shunts on jumpers JU6–JU9, and
measure the outputs at the OUTA and OUTB SMA con-
nectors. Table 3 lists the jumper configuration for the
DAC output mode selection.
Output DC Offset
The MAX5858A EV kit features an option to add a DC
offset to the analog output signals. To add a DC offset,
remove jumper JU2 and connect an appropriate DC
source across jumper JU2. The DC source has to be
able to sink at least 40mA of DC current. The DC offset
must be within 0 to 1.25V.
Interleaved Data Mode
The MAX5858A, MAX5858, and MAX5856A feature an
interleaved data mode that multiplexes the data inputs
of both channels through port A. This feature allows the
user to reduce the bit width of the input data bus. In
interleaved data mode, channel B data is latched on
the falling edge of the clock (CLK), and channel A data
is latched on the following rising edge of the clock
(CLK). Jumper JU3 sets the interleaved data mode
option. Table 4 lists the jumper selection.
SHUNTS
POSITION
DAC OUTPUT
MODE
ANALOG OUTPUT
LOCATIONS
Installed
Differential mode
OUTA and OUTB SMA
connectors
Not installed
Single-ended
mode
A+, A- and B+, B-
2-pin headers
Table 3. DAC Output Mode (Jumpers
JU6–JU9)
SHUNT
POSITION
MAX5858A IDE PIN
INTERLEAVED
DATA MODE
Not installed
Connected to DVDD
with R26
Enabled
Installed
Connected to DGND
Disabled
Table 4. Interleaved Data Mode (Jumper
JU3)
SHUNT
POSITION
MAX5858A
REN
PIN
REFERENCE
VOLTAGE OPTION
Not installed
Connected to AVDD
with R30
External reference
Installed
Connected to AGND
Internal reference
Table 5. Reference Voltage Option
(Jumper JU5)