參數(shù)資料
型號: MAX5865ETM
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 無繩電話/電話
英文描述: Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End
中文描述: TELECOM, CELLULAR, RF AND BASEBAND CIRCUIT, QCC48
封裝: 7 X 7 MM, 0.80 MM HEIGHT, TQFN-48
文件頁數(shù): 12/26頁
文件大?。?/td> 2144K
代理商: MAX5865ETM
M
Ultra-Low-Power, High-Dynamic-
Performance, 40Msps Analog Front End
12
______________________________________________________________________________________
PIN
NAME
FUNCTION
1
REFP
Upper Reference Voltage. Bypass with a 0.33μF capacitor to GND as close to REFP as possible.
2, 8, 43
V
DD
Analog Supply Voltage. Bypass V
DD
to GND with a combination of a 2.2μF capacitor in parallel with a
0.1μF capacitor.
3
IA+
Channel IA Positive Analog Input. For single-ended operation, connect signal source to IA+.
4
IA-
Channel IA Negative Analog Input. For single-ended operation, connect IA- to COM.
5, 7, 12, 37,
42
GND
Analog Ground. Connect all pins to GND ground plane.
6
CLK
Conversion Clock Input. Clock signal for both ADCs and DACs.
9
QA-
Channel QA Negative Analog Input. For single-ended operation, connect QA- to COM.
10
QA+
Channel QA Positive Analog Input. For single-ended operation, connect signal source to QA+.
11, 33, 39
V
DD
Analog Supply Voltage. Connect to V
DD
power plane as close to the device as possible.
13
16, 19
22
DA0
DA7
ADC Tri-State Digital Output Bits. DA7 is the most significant bit (MSB), and DA0 is the least
significant bit (LSB).
17
OGND
Output Driver Ground
18
OV
DD
Output Driver Power Supply. Supply range from +1.8V to V
DD
to accommodate most logic levels.
Bypass OV
DD
to OGND with a combination of a 2.2μF capacitor in parallel with a 0.1μF capacitor.
23
32
DD0
DD9
DAC Digital Input Bits. DD9 is the MSB, and DD0 is the LSB.
34
DIN
3-Wire Serial Interface Data Input. Data is latched on the rising edge of the SCLK.
35
SCLK
3-Wire Serial Interface Clock Input
36
CS
3-Wire Serial Interface Chip Select Input. Apply logic low enables the serial interface.
38
N.C.
No Connection
40, 41
QD+, QD-
DAC Channel-QD Differential Voltage Output
44, 45
ID-, ID+
DAC Channel-ID Differential Voltage Output
46
REFIN
Reference Input. Connect to V
DD
for internal reference.
47
COM
Common-Mode Voltage I/O. Bypass COM to GND with a 0.33μF capacitor.
48
REFN
Negative Reference I/O. Conversion range is
±
(V
REFP
- V
REFN
). Bypass REFN to GND with a 0.33μF
capacitor.
EP
Exposed Paddle. Exposed paddle is internally connected to GND. Connect EP to the GND plane.
Pin Description
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