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參數(shù)資料
| 型號(hào)： | MAX5856AECM+D |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 9/23頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8BIT DUAL 300MSPS 48-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 設(shè)置時(shí)間： | 11ns |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 792mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP 裸露焊盤（7x7） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 2 電流，單極 |
| 采樣率（每秒）： | 300M |
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MAX5856A
Dual 8-Bit, 300Msps DAC with 4x/2x/1x
Interpolation Filters and PLL
______________________________________________________________________________________
17
PLL Clock Multiplier and
Clocking Modes
The MAX5856A features an on-chip PLL clock multipli-
er, which generates all internal, synchronized high-
speed clock signals required by the input data latches,
interpolation filters, and DAC cores. The on-chip PLL
includes a phase detector, VCO, prescalar, and
charge-pump circuits. The PLL can be enabled or dis-
abled through PLLEN. To enable PLL, set PLLEN = 1.
With the PLL enabled (PLLEN = 1) and 4x/2x interpola-
tion enabled, an external low-frequency clock reference
source may be applied to CLK pin. The clock reference
source serves as the input data clock. The on-chip PLL
multiplies the clock reference by a factor of two (2x) or
a factor of four (4x). The input data rate range and CLK
frequency are set by the selected interpolation mode.
In 2x interpolation mode, the data rate range is 75MHz
to 150MHz. In 4x interpolation mode, the data rate
range is 37.5MHz to 75MHz.
Note: When the PLL is enabled, CLK becomes an
input, requiring CLKXP to be pulled low and CLKXN to
be pulled high. To obtain the best phase noise perfor-
mance, disable the PLL function.
With the PLL disabled (PLLEN = 0) and 4x/2x interpola-
tion enabled, an external conversion clock is applied at
CLKXN/CLKXP. The conversion clock at CLKXN/CLKXP
has a frequency range of 0 to 300MHz (see Table 5).
This clock is buffered and distributed by the
MAX5856A to drive the interpolation filters and DAC
cores. In this mode, CLK becomes a divide-by-N (DIV-
N) output at either a divide-by-two or divide-by-four
rate. The DIV-N factor is set by the selected interpola-
tion mode. The CLK output, at DIV-N rate, must be
used to synchronize data into the MAX5856A data
ports. In this mode, keep the capacitive load at the CLK
output low (10pF or less at fDAC = 165MHz).
With the interpolation disabled (1x mode) and the PLL
disabled (PLLEN = 0), the input clock at CLKXN/CLKXP
can be used to directly update the DAC cores. In this
mode, the maximum data rate is 165MHz.
Internal Reference and Control Amplifier
The MAX5856A provides an integrated 50ppm/°C,
1.24V, low-noise bandgap reference that can be dis-
abled and overridden with an external reference volt-
age. REFO serves either as an external reference input
or an integrated reference output. If REN is connected
to AGND, the internal reference is selected and REFO
provides a 1.24V (50A) output. Buffer REFO with an
external amplifier, when driving a heavy load.
The MAX5856A also employs a control amplifier
designed to simultaneously regulate the full-scale out-
put current (IFS) for both outputs of the devices.
Calculate the output current as:
IFS = 32 x IREF
where IREF is the reference output current (IREF =
VREFO/RSET) and IFS is the full-scale output current.
RSET is the reference resistor that determines the
amplifier output current of the MAX5856A (Figure 4).
This current is mirrored into the current-source array
where IFS is equally distributed between matched cur-
rent segments and summed to valid output current
readings for the DACs.
IFS
CCOMP*
REFR
IREF
REFO
MAX4040
1.24V
BANDGAP
REFERENCE
CURRENT-
SOURCE ARRAY
*COMPENSATION CAPACITOR (CCOMP ≈ 100nF)
OPTIONAL EXTERNAL BUFFER
FOR HEAVIER LOADS
REN
MAX5856A
IREF =
VREF
RSET
AGND
Figure 4. Setting IFS with the Internal 1.24V Reference and the Control Amplifier
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX5856AECM-TD | 功能描述:數(shù)模轉(zhuǎn)換器- DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX5858AECM | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| MAX5858AECM+D | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 10-Bit 2Ch 300Msps DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX5858AECM+TD | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 10-Bit 2Ch 300Msps DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX5858AECM-D | 功能描述:數(shù)模轉(zhuǎn)換器- DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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