參數(shù)資料
型號(hào): MAX5852
廠商: Maxim Integrated Products, Inc.
英文描述: Quadruple 2-Input Exclusive-OR Gates 14-CDIP -55 to 125
中文描述: 雙路、8位、165Msps、電流輸出DAC
文件頁(yè)數(shù): 10/18頁(yè)
文件大?。?/td> 1290K
代理商: MAX5852
M
Dual, 8-Bit, 165Msps, Current-Output DAC
10
______________________________________________________________________________________
Pin Description
PIN
1
2
3
NAME
DA7/PD
DA6/DACEN Channel A Input Data Bit 6/DAC Enable Control
DA5/IDE
Channel A Input Data Bit 5/Interleaved Data Enable
FUNCTION
Channel A Input Data Bit 7 (MSB)/Power-Down
4
DA4/
REN
Channel A Input Data Bit 4/Reference Enable. Setting
REN
= 0 enables the internal reference. Setting
REN
= 1 disables the internal reference.
5
6
7
8
DA3/G3
DA2/G2
DA1/G1
DA0/G0
Channel A Input Data Bit 3/Channel A Gain Adjustment Bit 3
Channel A Input Data Bit 2/Channel A Gain Adjustment Bit 2
Channel A Input Data Bit 1/Channel A Gain Adjustment Bit 1
Channel A Input Data Bit 0 (LSB)/Channel A Gain Adjustment Bit 0
9, 10, 21,
22
N.C.
No Connection. Do not connect to these pins.
11
12
13
14
15
16
17
18
19
20
23
DB7
DB6
DB5
DB4
DB3
DV
DD
DGND
DB2
DB1
DB0
CW
Channel B Input Data Bit 7 (MSB)
Channel B Input Data Bit 6
Channel B Input Data Bit 5
Channel B Input Data Bit 4
Channel B Input Data Bit 3
D g al P ow er Inp ut. S ee the
P ow er S up p es, Byp assi ng D ecoup ng and Layout
secti on for m or e d etai s.
Digital Ground
Channel B Input Data Bit 2
Channel B Input Data Bit 1
Channel B Input Data Bit 0 (LSB)
Active-Low Control Word Write Pulse. The control word is latched on the rising edge of
CW
.
24
DCE
Active-Low Differential Clock Enable Input. Drive
DCE
low to enable differential clock inputs
CLKXP and CLKXN. Drive
DCE
high to disable the differential clock inputs and enable the single-
ended CLK input.
25
CLKXP
Positive Differential Clock Input. With
DCE
= 0, CLKXP and CLKXN are enabled. With
DCE
= 1, CLKXP
and CLKXN are disabled. Connect CLKXP to CGND when the differential clock is disabled.
26
CLKXN
Negative Differential Clock Input. With
DCE
= 0, CLKXP and CLKXN are enabled. With
DCE
= 1, CLKXP
and CLKXN are disabled. Connect CLKXN to CV
DD
when the differential clock is disabled.
Clock Power Input. See the
Power Supplies, Bypassing, Decoupling, and Layout
section for more details.
27, 30
CV
DD
28
CLK
Single-Ended Clock Input/Output. With the differential clock disabled (
DCE
= 1), CLK becomes a single-
ended conversion clock input. With the differential clock enabled (
DCE
= 0), CLK is a single-ended
output that mirrors differential clock inputs CLKXP and CLKXN. See the
Clock Modes
section for more
information on CLK.
29
CGND
Clock Ground
31
REFO
Reference Input/Output. REFO serves as a reference input when the internal reference is disabled. If the
internal 1.24V reference is enabled, REFO serves as an output for the internal reference. When the
internal reference is enabled, bypass REFO to AGND with a 0.1μF capacitor.
相關(guān)PDF資料
PDF描述
MAX5852ETL Quadruple 2-Input Exclusive-OR Gates 14-CFP -55 to 125
MAX5858 Quadruple 2-Input Exclusive-OR Gates 14-CDIP -55 to 125
MAX5858ECM Dual, 10-Bit, 300Msps, Current-Output DAC with 4x/2x/1x Interpolation Filters
MAX5863 Quadruple Differential Line Receiver 16-CDIP -55 to 125
MAX5863ETM 5V High-Speed RS-232 Transceivers with 0.1uF Capacitors
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