參數(shù)資料
型號: MAX5851ETL+
廠商: Maxim Integrated Products
文件頁數(shù): 5/18頁
文件大小: 0K
描述: IC DAC 8BIT DUAL 80MSPS 40-TQFN
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 50
設置時間: 12ns
位數(shù): 8
數(shù)據(jù)接口: 并聯(lián)
轉換器數(shù)目: 2
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 40-WFQFN 裸露焊盤
供應商設備封裝: 40-TQFN-EP(6x6)
包裝: 管件
輸出數(shù)目和類型: 4 電流,單極
采樣率(每秒): 80M
MAX5851
Dual, 8-Bit, 80Msps, Current-Output DAC
______________________________________________________________________________________
13
IFS
CCOMP*
REFR
IREF
REFO
MAX4040
1.24V
BANDGAP
REFERENCE
CURRENT-
SOURCE
ARRAY
*COMPENSATION CAPACITOR (CCOMP ≈ 100nF)
OPTIONAL EXTERNAL BUFFER
FOR HEAVIER LOADS
MAX5851
IREF =
VREF
RSET
AGND
REN = 0
Figure 3. Setting IFS with the Internal 1.24V Reference and the
Control Amplifier
Internal Reference and Control Amplifier
The MAX5851 provides an integrated 50ppm/°C, 1.24V,
low-noise bandgap reference that can be disabled and
overridden with an external reference voltage. REFO
serves either as an external reference input or an inte-
grated reference output. If REN = 0, the internal refer-
ence is selected and REFO provides a 1.24V (50A)
output. Buffer REFO with an external amplifier when dri-
ving a heavy load.
The MAX5851 also employs a control amplifier
designed to simultaneously regulate the full-scale out-
put current (IFS) for both outputs of the devices.
Calculate the output current as:
IFS = 32 IREF
where IREF is the reference output current (IREF =
VREFO / RSET) and IFS is the full-scale output current. RSET
is the reference resistor that determines the amplifier out-
put current of the MAX5851 (Figure 3). This current is mir-
rored into the current-source array where IFS is equally
distributed between matched current segments and
summed to valid output current readings for the DACs.
External Reference
To disable the internal reference of the MAX5851, set
REN = 1. Apply a temperature-stable, external reference
to drive the REFO pin and set the full-scale output
(Figure 4). For improved accuracy and drift performance,
choose a fixed-output voltage reference such as the
1.2V, 25ppm/°C MAX6520 bandgap reference.
Detailed Timing
The MAX5851 accepts an input data and DAC con-
version rate of up to 80Msps. The input latches on the
rising edge of the clock, whereas the output latches
on the following rising edge.
Figure 5 depicts the write cycle of the two DACs in non-
interleaved mode.
The MAX5851 can also operate in an interleaved data
mode. Programming the IDE bit with a high level activates
this mode (Tables 1 and 2). In interleaved mode, data for
both DAC channels is written through input port A.
Channel B data is written on the falling edge of the clock
signal and then channel A data is written on the following
rising edge of the clock signal. Both DAC outputs (chan-
nel A and B) are updated simultaneously on the next fol-
lowing rising edge of the clock. The interleaved data
mode is attractive for applications where lower data rates
are acceptable and interfacing on a single 8-bit bus is
desired (Figure 6).
AVDD
EXTERNAL
1.2V
REFERENCE
MAX6520
AGND
0.1F
10F
AVDD
AGND
IFS
REFR
IREF
REFO
1.24V
BANDGAP
REFERENCE
CURRENT-
SOURCE
ARRAY
MAX5851
RSET
AGND
REN = 1
Figure 4. MAX5851 with External Reference
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