參數(shù)資料
型號(hào): MAX5841MEUB+
廠商: Maxim Integrated Products
文件頁數(shù): 4/15頁
文件大?。?/td> 0K
描述: IC DAC 10BIT QUAD 2WIRE 10-UMAX
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 50
設(shè)置時(shí)間: 4µs
位數(shù): 10
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 4
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-µMAX
包裝: 管件
輸出數(shù)目和類型: 4 電壓,單極
采樣率(每秒): *
產(chǎn)品目錄頁面: 1398 (CN2011-ZH PDF)
MAX5841
Quad, 10-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
12
______________________________________________________________________________________
SERIAL DATA INPUT
C3
C2
C1
C0
D9
D8
D7
D6
FUNCTION
00
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
Load DAC A input and DAC registers with new data.
Contents of DAC B, C, and D input registers are transferred
to the respective DAC registers. All outputs are updated.
00
01
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
Load DAC B input and DAC registers with new data.
Contents of DAC A, C, and D input registers are transferred
to the respective DAC registers. All outputs are updated.
00
10
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
Load DAC C input and DAC registers with new data.
Contents of DAC A, B, and D input registers are transferred
to the respective DAC registers. All outputs are updated.
00
11
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
Load DAC D input and DAC registers with new data.
Contents of DAC A, B, and C input registers are transferred
to the respective DAC registers. All outputs are updated
simultaneously.
01
00
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
Load DAC A input register with new data. DAC outputs
remain unchanged.
01
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
Load DAC B input register with new data. DAC outputs
remain unchanged.
01
10
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
Load DAC C input register with new data. DAC outputs
remain unchanged.
01
11
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
Load DAC D input register with new data. DAC outputs
remain unchanged.
10
00
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
Data in all input registers is transferred to respective DAC
registers. All DAC outputs are updated simultaneously. New
data is loaded into DAC A input register.
10
01
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
Data in all input registers is transferred to respective DAC
registers. All DAC outputs are updated simultaneously. New
data is loaded into DAC B input register.
10
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
Data in all input registers is transferred to respective DAC
registers. All DAC outputs are updated simultaneously. New
data is loaded into DAC C input register.
10
11
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
Data in all input registers is transferred to respective DAC
registers. All DAC outputs are updated simultaneously. New
data is loaded into DAC D input register.
11
00
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
Load all DACs with new data and update all DAC outputs
simultaneously. Input and DAC registers are updated with
new data.
11
01
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
Load all input registers with new data. DAC outputs remain
unchanged.
Table 3. Command Byte Definitions
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