參數(shù)資料
型號(hào): MAX5812
廠商: Maxim Integrated Products, Inc.
英文描述: 12-Bit Low-Power, 2-Wire, Serial Voltage-Output DAC
中文描述: 12位、低功耗、2線、串行電壓輸出DAC
文件頁(yè)數(shù): 3/13頁(yè)
文件大?。?/td> 268K
代理商: MAX5812
M
12-Bit Low-Power, 2-Wire, Serial
Voltage-Output DAC
_______________________________________________________________________________________
3
Note 1:
All devices are 100% production tested at T
A
= +25
°
C and are guaranteed by design for T
A
= T
MIN
to T
MAX
.
Note 2:
Static specifications are tested with the output unloaded.
Note 3:
Linearity is guaranteed from codes 115 to 3981.
Note 4:
Offset and gain error limit the FSR.
Note 5:
Guaranteed by design. Not production tested.
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +2.7V to +5.5V, GND = 0, R
L
= 5k
, C
L
= 200pF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at
V
DD
= +5V, T
A
= +25
°
C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
0.2
MAX
UNITS
nV-s
Digital Feedthrough
Code = 000 hex, digital inputs from 0 to V
DD
Major carry transition, code = 7FF hex to 800
hex and 800 hex to 7FF hex
Digital-to-Analog Glitch Impulse
12
nV-s
POWER SUPPLIES
Supply Voltage Range
V
DD
2.7
5.5
170
190
1
V
All digital inputs at 0 or V
DD
= 3.6V
All digital inputs at 0 or V
DD
= 5.5V
All digital inputs at 0 or V
DD
= 5.5V
100
130
0.3
Supply Current with No Load
μA
Power-Down Supply Current
TIMING CHARACTERISTICS (Figure 1)
Serial Clock Frequency
Bus Free Time Between STOP
and START Conditions
START Condition Hold Time
SCL Pulse Width Low
SCL Pulse Width High
Repeated START Setup Time
Data Hold Time
Data Setup Time
SDA and SCL Receiving
Rise Time
SDA and SCL Receiving
Fall Time
μA
f
SCL
0
400
kHz
t
BUF
1.3
μs
t
HD, STA
0.6
1.3
0.6
0.6
0
100
μs
μs
μs
μs
μs
ns
t
LOW
t
HIGH
t
SU, STA
t
HD, DAT
t
SU, DAT
0.9
t
r
(Note 5)
0
300
ns
t
f
(Note 5)
0
300
ns
SDA Transmitting Fall Time
t
f
(Note 5)
20 +
0.1C
b
0.6
250
ns
STOP Condition Setup Time
Bus Capacitance
Maximum Duration of
Suppressed Pulse Widths
t
SU-STO
C
b
μs
pF
(Note 5)
400
t
SP
0
50
ns
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