參數(shù)資料
型號: MAX5754UTN+
廠商: Maxim Integrated Products
文件頁數(shù): 7/25頁
文件大?。?/td> 0K
描述: IC DAC 14BIT 32CHAN SER 56-TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 37
設(shè)置時間: 20µs
位數(shù): 14
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 32
電壓電源: 模擬和數(shù)字
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 56-TQFN-EP(8x8)
包裝: 管件
輸出數(shù)目和類型: 32 電壓,單極
采樣率(每秒): *
MAX5753/MAX5754/MAX5755
32-Channel, 14-Bit, Voltage-Output
DACs with Serial Interface
______________________________________________________________________________________
15
Note: The offset DAC of every device can be pro-
grammed with any of the three output voltage ranges.
However, the specifications in the Electrical
Characteristics are only guaranteed (production tested)
for the offset code associated with each particular part
number. For example, the MAX5754 specifications are
only valid with the MAX5754 offset-DAC code shown in
Table 1.
The offset DAC is summed with GS (Figure 1). The offset
DAC can also cancel the offset of the output buffers.
Any change in the offset DAC affects all 32 DACs.
The offset DAC is also configured identically to the
other 32 DACs with an input and DAC register. Write to
the offset DAC through the serial interface by using
control bits C2, C1, and C0 = 001 followed by the data
bits D13–D0 and S1 and S0. The CLR command affects
the offset DAC as well as the other DACs.
The data format for the offset DAC codes are: control bits
C2, C1, and C0 = 011, address bits A5–A0 = 100000, 7
don’t-care bits, 14 data bits, and 2 empty bits; S1 and S0.
Set S1 and S0 to zero.
Output Amplifiers (OUT0–OUT31)
All DAC outputs are internally buffered. The internal
buffers provide gain, improved load regulation, and tran-
sition glitch suppression for the DAC outputs. The output
buffers slew at 1V/s and can drive 10k
in parallel with
100pF. The output buffers are powered by AVCC and
VSS. AVCC and VSS determine the maximum output
voltage range of the device.
The input code, the voltage reference, the offset DAC
output, the voltage on GS, and the gain of the output
amplifier determine the output voltage. Calculate VOUT
as follows:
where GAIN = 10/3 for the MAX5753/MAX5754/MAX5755.
Load-DAC (
LDAC) Input
The MAX5753/MAX5754/MAX5755 feature an active-
low LDAC logic input that allows the outputs OUT_ to
update asynchronously. Keep LDAC high during nor-
mal operation (when the device is controlled only
through the serial interface). Drive LDAC low to simulta-
neously update all DAC outputs with data from their
respective input registers. Figure 3 shows the LDAC
timing with respect to OUT_.
A software command can also activate the LDAC oper-
ation. To activate LDAC by software, set control bits
V
GAIN
V
DAC code
offset DAC code
V
OUT
REF
GS
=
××
()
+
2
14
PART
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
S1
S0
MAX5753
0000
000000000000
MAX5754
0100
000000000000
MAX5755
1000
000000000000
Table 1. Offset DAC Codes
OUT_
±0.5 LSB
tS
tLDAC
LDAC
Figure 3.
LDAC Timing
Note: For the MAX5753/MAX5754/MAX5755, the maximum code for the offset DAC is 10000.
Table 2. Serial Data Format
CONTROL
BITS
ADDRESS
BITS
DON’T-
CARE
BITS
DATA BITS*
C2, C1,
AND C0
A5–A0
D13–D0,
S1 AND S0
011
100000
XXXXXXX
See Table 1
*S1 and S0 are empty bits—set to zero.
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