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參數(shù)資料
| 型號(hào)： | MAX5742EUB |
| 廠(chǎng)商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類(lèi)： | DAC |
| 英文描述： | 12-Bit, Low-Power, Quad, Voltage-Output DAC with Serial Interface |
| 中文描述： | SERIAL INPUT LOADING, 4 us SETTLING TIME, 12-BIT DAC, PDSO10 |
| 封裝： | 5 X 3 MM, MO-187CBA, MICRO, SOP-10 |
| 文件頁(yè)數(shù)： | 3/15頁(yè) |
| 文件大小： | 676K |
| 代理商： | MAX5742EUB |
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M
12-Bit, Low-Power, Quad, Voltage-Output
DAC with Serial Interface
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +2.7V to +5.5V, GND = 0, V
REF
= V
DD
, R
L
= 5k
, C
L
= 200pF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are
V
DD
= +5V, T
A
= +25
°
C.)
TIMING CHARACTERISTICS
(V
DD
= 2.7V to 5.5V, GND = 0, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Note 1:
DC specifications are tested without output loads.
Note 2:
Linearity guaranteed from code 115 to code 3981.
Note 3:
Limited with test conditions.
Note 4:
Offset and gain error limit the FSR.
Note 5:
Guaranteed by design.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (SCLK, DIN,
CS
)
Input High Voltage
V
IH
V
DD
= +3V, +5V
0.7 x
V
DD
V
Input Low Voltage
V
IL
V
DD
= +3V, +5V
0.3 x
V
DD
±
1
V
Input Leakage Current
Input Capacitance
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
Voltage Output Settling Time
Digital Feedthrough
I
IN
C
IN
Digital inputs = 0 or V
DD
±
0.1
5
μA
pF
SR
0.5
4
0.1
V/μs
μs
nV-s
400 hex to C00 hex (Note 5)
Any digital inputs from 0 to V
DD
Major carry transition (code 7FF hex to code
800 hex)
10
Digital-Analog Glitch Impulse
12
nV-s
DAC-to-DAC Crosstalk
POWER REQUIREMENTS
Supply-Voltage Range
2.4
nV-s
V
DD
2.7
5.5
395
420
1
V
All digital inputs at 0 or V
DD
= 3.6V
All digital inputs at 0 or V
DD
= 5.5V
All digital inputs at 0 or V
DD
= 5.5V
229
271
0.29
Supply Current with No Load
I
DD
μA
Power-Down Supply Current
I
DDPD
μA
PARAMETER
SYMBOL
f
SCLK
t
CH
t
CL
t
CSS
t
CSH
t
DS
t
DH
t
CSW
CONDITIONS
MIN
0
25
25
10
10
15
0
80
TYP
MAX
20
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
SCLK Clock Frequency
SCLK Pulse Width High
SCLK Pulse Width Low
CS
Fall to SCLK Rise Setup Time
SCLK Fall to
CS
Rise Setup Time
DIN to SCLK Fall Setup Time
DIN to SCLK Fall Hold Time
CS
Pulse Width High
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