參數(shù)資料
型號(hào)： MAX5722EUA
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： DAC
英文描述： 12-Bit, Low-Power, Dual, Voltage-Output DAC with Serial Interface
中文描述： SERIAL INPUT LOADING, 4 us SETTLING TIME, 12-BIT DAC, PDSO8
封裝： 5 X 3 MM, MO-187CAA, MICRO, SOP-8
文件頁(yè)數(shù)： 9/14頁(yè)
文件大?。?/td> 686K
代理商： MAX5722EUA
M
12-Bit, Low-Power, Dual, Voltage-Output
DAC with Serial Interface
_______________________________________________________________________________________
9
Detailed Description
The MAX5722 contains two 12-bit, voltage-output, low-
power, digital-to-analog converters (DACs). Each DAC
employs a resistor string architecture that converts a
12-bit digital input word to an equivalent analog output
voltage proportional to the applied reference voltage.
The MAX5722 shares one reference input (REF)
between both DACs. The MAX5722 includes rail-to-rail
output buffer amplifiers for each DAC, and input logic
for simple microprocessor (μP), and CMOS interfaces.
The power-supply range is from +2.7V to +5.5V
(
Functional Diagram
). The MAX5722
’
s reference input
accepts a voltage range from 0 to V
DD
. In power-down
mode the reference input is high impedance. The
MAX5722 is compatible with the 3-wire SPI, QSPI,
MICROWIRE, and DSP serial interface with Schmitt-trig-
gered logic inputs.
Reference Input and DAC Output Range
The reference input accepts positive DC and AC sig-
nals. The voltage at REF sets the full-scale output volt-
age of both DACs. The reference input voltage range is
0 to V
DD
. The impedance at REF is 90k
. The voltage
at REF can vary from GND to V
DD
. The output voltages
(V
OUT_
) are represented by a digitally programmable
voltage source as:
V
OUT_
= (V
REF
D) / 2
12
where D is the decimal equivalent of binary DAC input
code ranging from 0 to 4095. V
REF
is the voltage at
REF.
Output Buffer Amplifiers
All DACs are internally buffered at the output. The
buffer amplifiers have both rail-to-rail common mode
and (GND to V
REF
) output voltage range. The buffers
are unity-gain stable with C
L
= 200pF and R
L
= 5k
.
Buffer amplifiers are disabled during power-up and
individual DAC outputs are shorted to GND through a
100k
resistor. Buffer amplifiers can individually or alto-
gether be powered-down by programming the input
register control bits. During power-down, contents of
the input and DAC registers remain the same. On
wake-up, all DAC outputs are restored to their pre-
power-down voltage values.
Power-Down Mode
In power-down mode, the DAC outputs are pro-
grammed to one of three output states, 1k
, 100k
, or
floating (Table 1). The REF input is high impedance
(2M
typ), to conserve current drain from the system
reference; therefore, the system reference does not
have to be powered-down. The DAC outputs return to
the values contained in the registers when brought out
of power-down. The recovery time, from total power-
down to power-up, is 8μs. This extra time is needed to
allow the internal bias to wake-up. Power-down mode
reduces current consumption to 0.3μA.
3-Wire Serial Interface
The MAX5722 digital interface is a standard 3-wire con-
nection compatible with SPI/QSPI/MICROWIRE/DSP
interfaces. The chip-select input (
CS
) frames the serial
data loading at DIN. Immediately following
CS
high-to-
low transition, the data is shifted synchronously and
latched into the input register on the falling edge of the
serial clock input (SCLK). After 16 bits have been
loaded into the serial input register, it transfers its con-
tents to the DAC latch.
CS
may then either be held low
or brought high.
CS
must be brought high for a mini-
mum of 80ns before the next write sequence, since a
write sequence is initiated on a falling edge of
CS
. Not
Pin Description
PIN
NAME
FUNCTION
1
V
DD
Power-Supply Input
2
GND
Ground
3
CS
Chip-Select Input
4
SCLK
Serial-Clock Input
5
DIN
Serial Data Input
6
REF
External Reference Voltage Input
7, 8
OUTA, OUTB
DAC Voltage Outputs. Power-on reset sets DAC register to zero, and internally connects
OUT to GND with 100k
resistor.
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