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參數資料
| 型號： | MAX5712AUT+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數： | 9/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC SERIAL 12BIT 1CH SOT23-6 |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 設置時間： | 4µs |
| 位數： | 12 |
| 數據接口： | 串行 |
| 轉換器數目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 727mW |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-6 |
| 供應商設備封裝： | SOT-6 |
| 包裝： | 帶卷 (TR) |
| 輸出數目和類型： | 1 電壓，單極 |
| 采樣率（每秒）： | * |
MAX5712
12-Bit, Low-Power, Rail-to-Rail
Voltage-Output Serial DAC in SOT23
8
Maxim Integrated
Shutdown Modes
The MAX5712 includes three software-controlled shut-
down modes that reduce the supply current to below
1A. In two of the three shutdown modes, OUT is con-
nected to GND through a resistor. Table 1 lists the
three shutdown modes of operation.
Applications Information
Device Powered by an
External Reference
The MAX5712 generates an output voltage proportional
to VDD, coupling power supply noise to the output. The
circuit in Figure 2 rejects this power-supply noise by
powering the device directly with a precision voltage
reference, improving overall system accuracy. The
MAX6030 (+3V, 75ppm) or the MAX6050 (+5V, 75ppm)
precision voltage references are ideal choices due to
the low-power requirements of the MAX5712. This solu-
tion is also useful when the required full-scale output
voltage is less than the available supply voltages.
Digital Inputs and Interface Logic
The 3-wire digital interface for the MAX5712 is compati-
ble with SPI, QSPI, MICROWIRE, and DSP. The three
digital inputs (CS, DIN, and SCLK) load the digital input
serially into the DAC. All of the digital inputs include
Schmitt-trigger buffers to accept slow-transition inter-
faces. This allows optocouplers to interface directly to
the MAX5712 without additional external logic. The digi-
tal inputs are compatible with CMOS-logic levels.
Power-Supply Bypassing and Layout
Careful PC board layout is important for optimal system
performance. Keep analog and digital signals separate
to reduce noise injection and digital feedthrough. Use a
ground plane to ensure that the ground return from
GND to the supply ground is short and low impedance.
Bypass VDD with a 0.1F capacitor to ground as close
as possible to the device.
Chip Information
PROCESS: BiCMOS
16-BIT SERIAL WORD
MSB
LSB
MODE
OUTPUT
C3
C2
C1
C0
D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00
0
12-Bit DAC Code
Set and update
DAC
VOUT = VDD x
CODE/4096
1
XXXXXXXXXX
0
Wake-Up
Current DAC
setting (initially 0)
1
XXXXXXXXXX
0
1
Power-Down
Floating
1
XXXXXXXXXX
1
0
Power-Down
1k
Ω to GND
1
XXXXXXXXXX
1
Power-Down
100k
Ω to GND
Table 1. Serial Interface Mapping
VDD
GND
OUT
GND
OUT
MAX6050
MAX6030
MAX5712
IN
Figure 2. MAX5712 Powered By Reference
GND
SCLK
DIN
1
6
OUT
5
VDD
MAX5712
SOT23
TOP VIEW
2
34
CS
Pin Configuration
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