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參數(shù)資料
| 型號： | MAX5711EUT+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC SERIAL 10BIT 1CH SOT23-6 |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時間： | 4µs |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 727mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-6 |
| 供應(yīng)商設(shè)備封裝： | SOT-6 |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸出數(shù)目和類型： | * |
| 采樣率（每秒）： | * |
| 其它名稱： | MAX5711EUT+TDKR |
-4
-2
-3
0
-1
1
2
3
4
0
256 384
128
512 640 768 896 1024
MAX5711
toc01
CODE
INL
(LSB)
INTEGRAL NONLINEARITY
vs. CODE (TA = +25
°C)
VDD = +5V
VDD = +3V
MAX5711
10-Bit, Low-Power, Rail-to-Rail
Voltage-Output Serial DAC in SOT23
_______________________________________________________________________________________
3
Note 1: DC specifications are tested without output loads.
Note 2: Linearity guaranteed from code 29 to code 995.
Note 3: Offset and gain error limit the FSR.
Note 4: Guaranteed by design.
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.5V, GND = 0, RL = 5k
, CL = 200pF, TA = TMIN to TMAX, TA = +25°C, unless otherwise noted. Typical values are at
VDD = +5V, TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
SR
0.5
V/s
Voltage Output Settling Time
100 hex to 300 hex (Note 4)
4
10
s
Digital Feedthrough
Any digital inputs from 0 or VDD
0.2
nV-s
Digital-Analog Glitch Impulse
Major carry transition (code 1FF hex to code
200 hex)
12
nV-s
POWER REQUIREMENTS
Supply Voltage Range
VDD
2.7
5.5
V
All digital inputs at 0 or VDD, VDD = 3.6V
85
150
Supply Current with No Load
IDD
All digital inputs at 0 or VDD, VDD = 5.5V
105
187
A
Power-Down Supply Current
IDDPD
All digital inputs at 0 or VDD, VDD = 5.5V
0.29
1
A
TIMING CHARACTERISTICS (FIGURE 2) (Timing is tested with no load)
SCLK Clock Frequency
fSCLK
020
MHz
SCLK Pulse Width High
tCH
20
ns
SCLK Pulse Width Low
tCL
20
ns
CS Fall to SCLK Rise Setup
tCSS
15
ns
DIN Setup Time
tDS
15
ns
DIN Hold Time
tDH
0ns
SCLK Falling Edge to
CS Rising
Edge
tCSH
10
ns
CS Pulse Width High
tCSW
80
ns
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
-0.20
-0.10
-0.15
0
-0.05
0.05
0.10
0.15
0.20
0
256 384
128
512 640 768 896 1024
MAX5711
toc02
CODE
DNL
(LSB)
DIFFERENTIAL NONLINEARITY
vs. CODE (TA = +25
°C)
VDD = +3V OR +5V
-1.0
-0.6
-0.8
-0.2
-0.4
0.2
0
0.4
0.8
0.6
1.0
0
256 384
128
512 640 768 896 1024
MAX5711
toc03
CODE
TOTAL
UNADJUSTED
ERROR
(%)
TOTAL UNADJUSTED ERROR
vs. CODE (TA = +25
°C)
VDD = +5V
VDD = +3V
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