參數(shù)資料
型號: MAX5711AUT+T
廠商: Maxim Integrated Products
文件頁數(shù): 7/9頁
文件大?。?/td> 0K
描述: IC DAC 10BIT DUAL LP SER SOT23-6
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
設置時間: 4µs
位數(shù): 10
數(shù)據(jù)接口: 串行
轉換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 727mW
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: SOT-23-6
供應商設備封裝: SOT-6
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 1 電壓,單極
采樣率(每秒): *
其它名稱: Q4598528
MAX5711
10-Bit, Low-Power, Rail-to-Rail
Voltage-Output Serial DAC in SOT23
_______________________________________________________________________________________
7
Detailed Description
The MAX5711 voltage-output, 10-bit DAC, offers a full
10-bit performance in a small 6-pin SOT23 package.
The SOT23 footprint is less than 9mm2. The MAX5711
has less than 1LSB differential nonlinearity error, ensur-
ing monotonic performance. The device uses a simple
3-wire, SPI/QSPI/MICROWIRE and DSP-compatible ser-
ial interface that operates up to 20MHz. The MAX5711
incorporates three shutdown modes, making it ideal for
low-power applications.
Analog Section
The MAX5711 consists of a resistor string, an output
buffer, and a POR circuit. Monotonic digital-to-analog
conversion is achieved using a resistor string architec-
ture. Since VDD is the reference for the MAX5711, the
accuracy of the DAC depends on the accuracy of VDD.
The low bias current of the MAX5711 allows its power
to be supplied by a voltage reference such as the
MAX6030. The 10-bit DAC code is binary-unipolar with
1LSB = VDD/1024.
Output Buffer
The DAC output buffer has a rail-to-rail output and is
capable of driving a 5k
resistive load in parallel with a
200pF capacitive load. With a capacitive load of 200pF,
the output buffer slews 0.5V/s. With a 1/4FS to 3/4FS
output transition, the amplifier output settles to 1/2LSB
in less than 10s when loaded with 5k
in parallel with
200pF. The buffer amplifier is stable with any combination
of resistive loads greater than 5k
and capacitive loads
less than 200pF.
Program the input register bits to power-down the
device. The DAC registers are preserved during power-
down and upon wake-up, the DAC output is restored to
its pre-power-down voltage.
Power-On Reset
The MAX5711 has a POR circuit to set the DACs output
to zero when VDD is first applied. This ensures that
unwanted DAC output voltages will not occur immedi-
ately following a system startup, such as after a loss of
power. Upon initial power-up, an internal power-on
reset circuit ensures that all DAC registers are cleared,
the DAC is powered-down, and its output is terminated
to GND by a 100k
resistor. An 8s recovery time after
issuing a wake-up command is needed before writing
to the DAC registers.
Digital Section
3-Wire Serial Interface
The MAX5711 digital interface is a standard 3-wire con-
nection compatible with SPI/QSPI/MICROWIRE/DSP
interfaces. The chip-select input (
CS) frames the serial
data loading at DIN. Immediately following
CS high-to-
low transition, the data is shifted synchronously and
latched into the input register on the falling edge of the
serial clock input (SCLK). After 16 bits have been
loaded into the serial input register, the serial input reg-
ister transfers its contents to the DAC latch.
CS may
then either be held low or brought high.
CS must be
brought high for a minimum of 80ns before the next
write sequence, since a write sequence is initiated on a
tCH
tCL
tDH
tDS
tCSH
SO
C3
SCLK
CS
DIN
tCSS
tCSW
Figure 1. Timing Diagram
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