參數(shù)資料
型號(hào): MAX5580AEUP
廠(chǎng)商: MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi): DAC
英文描述: Quadruple Low-Power Differential Line Receiver 16-CFP -55 to 125
中文描述: SERIAL INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, PDSO20
封裝: 4.40 MM, MO-153ACT, TSSOP-20
文件頁(yè)數(shù): 31/34頁(yè)
文件大小: 1206K
代理商: MAX5580AEUP
M
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
______________________________________________________________________________________
31
Power-Supply and Layout Considerations
Bypass the analog and digital power supplies by using a
10μF capacitor in parallel with a 0.1μF capacitor to AGND
and DGND (Figure 10). Minimize lead lengths to reduce
lead inductance. Use shielding and/or ferrite beads to fur-
ther increase isolation.
Digital and AC transient signals coupling to AGND can
create noise at the output. Connect AGND to the high-
est quality ground available. Use proper grounding
techniques, such as a multilayer board with a low-
inductance ground plane. Wire-wrapped boards and
sockets are not recommended. For optimum system
performance, use PC boards with separate analog and
digital ground planes. Connect the two ground planes
together at the low-impedance power-supply source.
Using separate power supplies for AV
DD
and DV
DD
improves noise immunity. Connect AGND and DGND at
the low-impedance power-supply sources (Figure 11).
MAX5580–
MAX5585
10
μ
F
0.1
μ
F
DV
DD
AV
DD
DV
DD
AGND***
DGND***
10
μ
F
0.1
μ
F
AV
DD
1
μ
F**
0.1
μ
F**
MAX6126
REF
OUTA
FBA*
OUTB
FBB*
OUTC
FBC*
OUTD
FBD*
UPIO1
UPIO2
SCLK
DIN
PU
DSP
CS
*MAX5581/MAX5583/MAX5585 ONLY.
**REMOVE BYPASS CAPACITORS ON REF FOR AN AC REFERENCE INPUT.
***CONNECT ANALOG AND DIGITAL GROUND AT THE PLANES AT
THE LOW-IMPEDANCE POWER-SUPPLY SOURCE.
Figure 10. Bypassing Power Supplies AV
DD
, DV
DD
, and REF
MAX5580–MAX5585
0.1
μ
F
10
μ
F
AV
DD
AGND
AV
DD
AGND
0.1
μ
F
10
μ
F
DV
DD
DGND
DV
DD
DGND
DV
DD
DGND
ANALOG SUPPLY
DIGITAL SUPPLY
DIGITAL
CIRCUITRY
Figure 11. Separate Analog and Digital Power Supplies
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