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參數(shù)資料
| 型號(hào)： | MAX5556ESA+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 12/17頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC STEREO AUDIO 8-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | I²S，串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電壓，單極 |
| 采樣率（每秒）： | 50k |
| 產(chǎn)品目錄頁(yè)面： | 1397 (CN2011-ZH PDF) |
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MAX5556
Low-Cost Stereo Audio DAC
4
Maxim Integrated
ELECTRICAL CHARACTERISTICS (continued)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INTERNAL SCLK MODE
LRCLK Duty Cycle
(Note 7)
50
%
Internal SCLK Period
tISCLK
(Note 8)
1/fSCLK
ns
LRCLK Edge to Internal SCLK
tISCLKR
tISCLK/2
ns
tISDS
tMCLK + 10
SDATA Valid to Internal SCLK
Rising Setup Time
tISDH
MCLK period = tMCLK
tMCLK
ns
(VDD = +4.75V to +5.5V, VGND = 0V, ROUT_ = 10kΩ, COUT_ = 10pF, 0dBFS sine-wave signal at 997Hz, fLRCLK (fS) = 48kHz, fMCLK
= 12.288MHz, measurement bandwidth 10Hz to 20kHz, TA = -40°C to +85°C, outputs are unloaded, unless otherwise noted. Typical
values at VDD = +5V, TA = +25°C.) (Note 1)
Note 1: 100% production tested at TA = +85°C. Limits to -40°C are guaranteed by design.
Note 2: 0.5 LSB of triangular PDF dither added to data.
Note 3: Guaranteed by design, not production tested.
Note 4: PSRR test block diagram shown in Figure 1 denotes the test setup used to measure PSRR.
Note 5: Volume ramping interval starts from establishment of a valid MCLK to LRCLK ratio. Total time is proportional to the sample
rate (fS). 20ms based on 48ksps operation.
Note 6: In external SCLK mode, LRCLK duty cycles are not limited, provided all data formatting requirements are met. See Figure 4.
Note 7: The LRCLK duty cycle must be 50% ±1/2 MCLK period in internal SCLK mode.
Note 8: The SCLK/LRCLK ratio can be set to 32, 48, or 64, depending on the MCLK/LRCLK ratio selected. See Figure 4.
MCLK
SDATA
LRCLK
SCLK
ACTIVE
CLOCKS
GND
VDD
SPECTRUM
ANALYZER
LOUT, ROUT
ZG
AUDIO SIGNAL
GENERATOR
(100mVP-P AT 1kHz)
DC POWER SUPPLY
(5VDC)
MAX5556
+
-
Figure 1. PSRR Test Block Diagram
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX5556ESA/V+ | 功能描述:數(shù)模轉(zhuǎn)換器- DAC Low-Cost Stereo Audio DACs RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX5556ESA/V+T | 功能描述:數(shù)模轉(zhuǎn)換器- DAC Low-Cost Stereo Audio DACs RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX5556ESA+ | 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC 24-Bit 2Ch Audio DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| MAX5556ESA+ | 制造商:Maxim Integrated Products 功能描述:IC DAC 24BIT 50KSPS SOIC-8 |
| MAX5556ESA+T | 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC 24-Bit 2Ch Audio DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
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