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參數(shù)資料
| 型號： | MAX5550 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Quadruple Low-Power Differential Line Receiver 20-LCCC -55 to 125 |
| 中文描述： | 雙路、10位、可編程、可提供30mA高輸出電流的DAC |
| 文件頁數(shù)： | 4/15頁 |
| 文件大小： | 397K |
| 代理商： | MAX5550 |
M
Dual, 10-Bit, Programmable, 30mA
High-Output-Current DAC
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +2.7V to +5.25V, GND = 0, V
REFIN
= +1.25V, internal reference, R
FSADJ_
= 20k
; compliance voltage = (V
DD
- 0.6V),
V
SCLK/SCL
= 0, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at V
DD
= +3.0V and T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Bus Free Time Between a STOP
and START Condition
t
BUF
1.3
μs
Setup Time for STOP Condition
t
SU:STO
160
ns
Maximum Capacitive Load for
Each Bus Line
C
B
400
pF
SPI TIMING CHARACTERISTICS (Figure 6)
SCLK Clock Period
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS
Fall to SCLK Rise Setup Time
SCLK Rise to
CS
Rise Hold Time
DIN Setup Time
DIN Hold Time
SCLK Fall to DOUT Transition
CS
Fall to DOUT Enable
CS
Rise to DOUT Disable
SCLK Rise to
CS
Fall Delay
CS
Rise to SCLK Rise Hold Time
CS
Pulse-Width High
SPI TIMING CHARACTERISTICS FOR DAISY CHAINING (Figure 6)
SCLK Clock Period
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS
Fall to SCLK Rise Setup Time
SCLK Rise to
CS
Rise Hold Time
DIN Setup Time
DIN Hold Time
SCLK Fall to DOUT Transition
CS
Fall to DOUT Enable
CS
Rise to DOUT Disable
SCLK Rise to
CS
Fall Delay
CS
Rise to SCLK Rise Hold Time
CS
Pulse-Width High
t
CP
t
CH
t
CL
t
CSS
t
CSH
t
DS
t
DH
t
DO1
t
CSE
t
CSD
t
CS0
t
CS1
t
CSW
100
40
40
25
50
40
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
LOAD
= 30pF
C
LOAD
= 30pF
C
LOAD
= 30pF
40
40
40
50
40
100
t
CP
t
CH
t
CL
t
CSS
t
CSH
t
DS
t
DH
t
DO1
t
CSE
t
CSD
t
CS0
t
CS1
t
CSW
200
80
80
25
50
40
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
LOAD
= 30pF
C
LOAD
= 30pF
C
LOAD
= 30pF
40
40
40
50
40
100
Note 1:
100% production tested at T
A
= +25°C. Limits over temperature are guaranteed by design.
Note 2:
INL linearity is guaranteed from code 60 to code 1024.
Note 3:
Connect a resistor from FSADJ_ to GND to adjust the full-scale current. See the
Reference Architecture and Operation
section.
Note 4:
Settling time is measured from (0.25 x full scale) to (0.75 x full scale).
Note 5:
The device draws higher supply current when the digital inputs are driven with voltages between (V
DD
- 0.5V) and (GND +
0.5V). See the Supply Current vs. Digital Input Voltage graph in the
Typical Operating Characteristics
.
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