參數(shù)資料
型號(hào)： MAX5548
廠商： Maxim Integrated Products, Inc.
英文描述： Dual, 8-Bit, Programmable, 30mA High-Output-Current DAC
中文描述： 雙路、8位、可編程、可提供30mA高輸出電流的DAC
文件頁(yè)數(shù)： 3/15頁(yè)
文件大小： 296K
代理商： MAX5548
M
Dual, 8-Bit, Programmable, 30mA
High-Output-Current DAC
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +2.7V to +5.25V, GND = 0, V
REFIN
= +1.25V, internal reference, R
FSADJ_
= 20k
; compliance voltage = (V
DD
- 0.6V),
V
SCLK/SCL
= 0, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at V
DD
= +3.0V and T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
2
400
10
MAX
UNITS
%
DAC-to-DAC Current Matching
V
DD
= +3V, R
L
= 65
, C
L
= 24pF
V
DD
= +5V, no load
Wake-Up Time
μs
POWER SUPPLIES
Supply Voltage
Supply Current
Shutdown Current
LOGIC AND CONTROL INPUTS
V
DD
I
DD
+2.70
+5.25
6
1.2
V
V
DD
= +5.25V, no load
3
mA
μA
+2.7V
≤
V
DD
≤
+3.4V
0.7 x
V
DD
2.4
Input High Voltage (Note 5)
V
IH
+34V < V
DD
≤
+5.25V
(Note 5)
V
Input Low Voltage
V
IL
0.8
V
Input Hysteresis
V
HYS
0.1 x
V
DD
10
V
Input Capacitance
Input Leakage Current
Output Low Voltage
C
IN
I
IN
V
OL
pF
μA
V
±1
0.6
I
SINK
= 3mA
Output High Voltage
V
OH
I
SOURCE
= 2mA
V
DD
-
0.5
V
I
2
C TIMING CHARACTERISTICS (Figure 2)
SCL Clock Frequency
Setup Time for START Condition
Hold Time for START Condition
SCL Pulse-Width Low
SCL Pulse-Width High
Data Setup Time
Data Hold Time
f
SCL
t
SU:STA
t
HD:STA
t
LOW
t
HIGH
t
SU:DAT
t
HD:DAT
400
kHz
ns
ns
ns
ns
ns
ns
600
600
130
600
100
0
70
SCL Rise Time
t
RCL
20 + 0.1
x C
B
300
ns
SCL Fall Time
t
FCL
20 + 0.1
x C
B
300
ns
SDA Rise Time
t
RDA
20 + 0.1
x C
B
300
ns
SDA Fall Time
t
FDA
20 + 0.1
x C
B
300
ns
Bus Free Time Between a STOP
and START Condition
t
BUF
1.3
μs
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