參數(shù)資料
型號: MAX5544CSA+
廠商: Maxim Integrated Products
文件頁數(shù): 6/8頁
文件大小: 0K
描述: IC DAC 14BIT 5V SERIAL 8-SOIC
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 100
設置時間: 1µs
位數(shù): 14
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 1.5mW
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應商設備封裝: 8-SOIC
包裝: 管件
輸出數(shù)目和類型: 1 電壓,單極
采樣率(每秒): *
產(chǎn)品目錄頁面: 1397 (CN2011-ZH PDF)
MAX5544
Low-Cost, +5V, Serial-Input,
Voltage-Output, 14-Bit DAC
6
_______________________________________________________________________________________
;;
;;;;;;;;;
;;
tCSHO
tCH
tCSSO
tCL
tDH
tDS
tCSH1
tCSS1
CS
SCLK
DIN
D13
D12
S0
Figure 1. Timing Diagram
;
;;
CS
SCLK
DIN
MSB
LSB
D13
D6
D5 D4 D3 D2 D1 D0
S1 S0
SUB-BITS
DAC
UPDATED
D12 D11 D10 D9 D8 D7
Figure 2. 3-Wire Interface Timing Diagram
Detailed Description
The MAX5544 voltage-output, 14-bit digital-to-analog
converter (DAC) offers 14-bit monotonicity with less
than 1LSB differential linearity error. Serial-data transfer
minimizes the number of package pins required.
The MAX5544 is composed of two matched DAC sec-
tions, with a 12-bit inverted R-2R DAC forming the
12LSBs and the 4MSBs derived from 15 identically
matched resistors. This architecture allows the lowest
glitch energy to be transferred to the DAC output on
major-carry transitions. It also decreases the DAC out-
put impedance by a factor of eight compared to a stan-
dard R-2R ladder, allowing unbuffered operation in
medium-load applications. Figure 1 is the timing dia-
gram.
Digital Interface
The MAX5544 digital interface is a standard 3-wire con-
nection compatible with SPI/QSPI/MICROWIRE inter-
faces. The chip-select input (CS) frames the serial data
loading at the data input pin (DIN). Immediately follow-
ing CS’s high-to-low transition, the data is shifted
synchronously and latched into the input register on the
rising edge of the serial-clock input (SCLK). After 16
data bits (14 data bits, plus two sub-bits set to zero)
have been loaded into the serial input register, it trans-
fers its contents to the DAC latch on CS’s low-to-high
transition (Figure 2). Note that if CS does not remain
low during the entire 16 SCLK cycles, data will be cor-
rupted. In this case, reload the DAC latch with a new
16-bit word.
External Reference
The MAX5544 operates with external voltage refer-
ences from 2V to 3V. The reference voltage determines
the DAC’s full-scale output voltage.
Power-On Reset
The MAX5544 has a power-on reset circuit to set the
DAC’s output to 0V in unipolar mode when VDD is first
applied. This ensures that unwanted DAC output volt-
ages will not occur immediately following a system
power-up, such as after power loss. In bipolar mode,
the DAC output is set to -VREF.
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