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參數(shù)資料
| 型號： | MAX5514 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Dual. Ultra-Low-Power. 8-Bit. Voltage-Output DACs |
| 中文描述： | 雙路、超低功耗、8位、電壓輸出DAC |
| 文件頁數(shù)： | 5/23頁 |
| 文件大小： | 1544K |
| 代理商： | MAX5514 |
M
Dual, Ultra-Low-Power,
8-Bit, Voltage-Output DACs
_______________________________________________________________________________________
5
Note 1:
Linearity is tested within codes 6 to 255.
Note 2:
Offset is tested at code 6.
Note 3:
Gain is tested at code 255. For the MAX5514/MAX5515, FB_ is connected to its respective OUT_.
Note 4:
Guaranteed by design. Not production tested.
Note 5:
V
DD
must be a minimum of 1.8V.
Note 6:
Outputs can be shorted to V
DD
or GND indefinitely, provided that package power dissipation is not exceeded.
Note 7:
Optimal noise performance is at 2nF load capacitance.
Note 8:
Thermal hysteresis is defined as the change in the initial +25°C output voltage after cycling the device from T
MAX
to T
MIN
.
Note 9:
All digital inputs at V
DD
or GND.
Note 10:
Load = 10k
in parallel with 100pF, V
DD
= 5V, VREF = 4.096V (MAX5512/MAX5514) or V
REF
= 3.9V (MAX5513/MAX5515).
TIMING CHARACTERISTICS
(V
DD
= +4.5V to +5.5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS (V
DD
= 4.5V to 5.5V )
Serial Clock Frequency
DIN to SCLK Rise Setup Time
DIN to SCLK Rise Hold Time
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS
Pulse-Width High
SCLK Rise to
CS
Rise Hold Time
CS
Fall to SCLK Rise Setup Time
SCLK Fall to
CS
Fall Setup
CS
Rise to SCK Rise Hold Time
f
t
DS
t
DH
t
CH
t
CL
t
CSW
t
CSH
t
CSS
t
CSO
t
CS1
0
15
0
24
24
100
0
20
0
20
16.7
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMING CHARACTERISTICS
(VDD = +1.8V to +5.5V, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25
°
C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS (V
DD
= 1.8V to 5.5V )
Serial Clock Frequency
DIN to SCLK Rise Setup Time
DIN to SCLK Rise Hold Time
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS
Pulse-Width High
SCLK Rise to
CS
Rise Hold Time
CS
Fall to SCLK Rise Setup Time
SCLK Fall to
CS
Fall Setup
CS
Rise to SCK Rise Hold Time
f
SCLK
t
DS
t
DH
t
CH
t
CL
t
CSW
t
CSH
t
CSS
t
CSO
t
CS1
0
24
0
40
40
150
0
30
0
30
10
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX5515 | Dual. Ultra-Low-Power. 8-Bit. Voltage-Output DACs |
| MAX5512EUA | Dual, Ultra-Low-Power, 8-Bit, Voltage-Output DACs |
| MAX5513EUA | Dual, Ultra-Low-Power, 8-Bit, Voltage-Output DACs |
| MAX5515ETC | 9-Channel Differential Transceiver 56-CFP -55 to 125 |
| MAX5541 | Low-Cost, +5V, Serial-Input, Voltage-Output, 16-Bit DAC |
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