參數(shù)資料
型號: MAX5422ETA+T
廠商: Maxim Integrated Products
文件頁數(shù): 10/11頁
文件大?。?/td> 0K
描述: IC POT DGTL 256-TAP NV 8-TDFN
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1
接片: 256
電阻(歐姆): 50k
電路數(shù): 1
溫度系數(shù): 標準值 35 ppm/°C
存儲器類型: 非易失
接口: 3 線串口
電源電壓: 2.7 V ~ 5.25 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-WDFN 裸露焊盤
供應商設備封裝: 8-TDFN-EP(3x3)
包裝: 標準包裝
其它名稱: MAX5422ETA+TDKR
MAX5422/MAX5423/MAX5424
(
CS), data clock (SCLK), and data in (DIN). Drive CS
low to enable the serial interface and clock data syn-
chronously into the shift register on each SCLK rising
edge.
The WRITE commands (C1, C0 = 00 or 01) require 16
clock cycles to clock in the command and data (Figure
2a). The COPY commands (C1, C0 = 10, 11) can use
either eight clock cycles to transfer the command bits
(Figure 2b) or 16 clock cycles with 8 data bits that are
disregarded by the device (Figure 2a).
After loading data into the shift register, drive
CS high
to latch the data into the appropriate potentiometer
control register and disable the serial interface. Keep
CS low during the entire serial-data stream to avoid
corruption of the data.
The serial-data timing for the potentiometer is shown in
Figures 1 and 2.
256-Tap, Nonvolatile, SPI-Interface,
Digital Potentiometers
8
_______________________________________________________________________________________
CLOCK EDGE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Bit name
C1
C0
D7
D6
D5
D4
D3
D2
D1
D0
Write wiper register
0
D7
D6
D5
D4
D3
D2
D1
D0
Write NV register
0
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Copy wiper register to NV
register
00
10
00
Copy NV register to wiper
register
00
11
00
Table 1. Register Map
1
2
3
4
5
6
7
8
9
10111213141516
D7
D6
D5
D4
D3
D2
D1
D0
C1
C0
SCLK
DIN
A) 16-BIT COMMAND/DATA WORD
12
34
5
6
78
C1
C0
SCLK
DIN
B) 8-BIT COMMAND WORD
CS
Figure 2. Digital-Interface Format
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