參數(shù)資料
型號: MAX5402EUA
廠商: Maxim Integrated Products
文件頁數(shù): 3/9頁
文件大?。?/td> 0K
描述: IC POT DIGITAL 256-TAP 8-UMAX
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 50
系列: µPoT
接片: 256
電阻(歐姆): 10k
電路數(shù): 1
溫度系數(shù): 標(biāo)準(zhǔn)值 35 ppm/°C
存儲器類型: 易失
接口: 3 線串行(芯片選擇)
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-uMAX
包裝: 管件
MAX5402
256-Tap, PoT, Low-Drift,
Digital Potentiometer
________________________________________________________________________________________
3
Note 1: Linearity is defined in terms of the H-to-L code-dependent resistance.
Note 2: The DNL and INL are measured with the potentiometer configured as a voltage-divider with H = VDD and L = 0. The wiper
terminal is unloaded and measured with an ideal voltmeter.
Note 3: The DNL and INL are measured with the potentiometer configured as a variable resistor. H is unconnected and L = 0. The
wiper terminal is driven with a source current of 200A at VDD = +3V and 400A at VDD = +5V.
Note 4: The wiper resistance is the worst value measured, injecting a current, IW = VDD/RHL into terminal W.
Note 5: Digital timing is guaranteed by design.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Pulse Width Low
tCL
40
ns
CS Fall to SCLK Rise Setup Time
tCSS
40
ns
SCLK Rise to
CS Rise Hold Time
tCSH
0ns
DIN Setup Time
tDS
40
ns
DIN Hold Time
tDH
0ns
SCLK Rise to
CS Fall Delay
tCS0
10
ns
CS Rise to SCLK Rise Hold
tCS1
40
ns
CS Pulse Width High
tCSW
100
ns
POWER SUPPLIES
Supply Voltage
VDD
2.7
5.5
V
VDD = +5V
0.8
5
A
Supply Current
IDD
CS = SCLK =
DIN = VDD
VDD = +2.7V
0.1
A
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V, VH = VDD, VL = 0, TA = TMIN to TMAX. Typical values are at VDD = +5V, TA = +25°C, unless otherwise noted.)
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