參數(shù)資料
型號: MAX5402EUA+
廠商: Maxim Integrated Products
文件頁數(shù): 6/9頁
文件大?。?/td> 0K
描述: IC POT DIGITAL 256-TAP 8-UMAX
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 50
系列: µPoT
接片: 256
電阻(歐姆): 10k
電路數(shù): 1
溫度系數(shù): 標準值 35 ppm/°C
存儲器類型: 易失
接口: 3 線串行(芯片選擇)
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-uMAX
包裝: 管件
MAX5402
256-Tap, PoT, Low-Drift,
Digital Potentiometer
6
_______________________________________________________________________________________
Detailed Description
The MAX5402 consists of 255 fixed resistors in series
between pins H and L. The potentiometer wiper (pin W)
can be programmed to access any one of the 256 dif-
ferent tap points on the resistor string. The MAX5402
has an SPI-compatible 3-wire serial data interface to
control the wiper tap position. This write-only interface
contains three inputs: Chip Select (CS), Data In (DIN),
and Data Clock (SCLK). When CS is taken low, data
from the DIN pin is synchronously loaded into the 8-bit
serial shift register on the rising edge of each SCLK
pulse (Figure 1). The MSB is shifted in first, as shown in
Figure 3. Note that if CS is not kept low during the entire
data stream, the data will be corrupted and the device
will need to be reloaded. After all 8 data bits have been
loaded into the shift register, they are latched into the
decoder once CS is taken high. The decoder switches
the potentiometer wiper to the tap position that corre-
sponds to the 8-bit input data. Each resistor cell is
10k
/255 or 39.2 for the MAX5402.
The MAX5402 features POR circuitry. This sets the
wiper to the midscale position at power-up by loading a
binary value of 128 into the 8-bit latch. The MAX5402
can be used as a variable resistor by connecting pin W
to either pin H or L.
POT REGISTER LOADED
1ST CLOCK PULSE
SCLK
DIN
MSB
LSB
D0
D1
D2
D3
D4
D5
D6
D7
8TH CLOCK PULSE
TIME
CS
Figure 1. Serial Interface Timing Diagram
SCLK
DIN
tCSO
tCSS
tCH
tCL
tDS
tDH
tCP
tCSH
tCS1
tCSW
CS
Figure 2. Detailed Serial Interface Timing Diagram
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