參數(shù)資料
型號(hào): MAX538
廠商: Maxim Integrated Products, Inc.
英文描述: +5V, Low-Power, Voltage-Output, Serial 12-Bit DACs(單通道,電壓輸出,12位串行D/A轉(zhuǎn)換器)
中文描述: +5V、低功耗、電壓輸出、串行12位DAC
文件頁數(shù): 8/16頁
文件大?。?/td> 174K
代理商: MAX538
M
5V, Low-Power, Voltage-Output
S erial 12-Bit DACs
8
_______________________________________________________________________________________
10
FUNCTION
1
BIPOFF
Bipolar offset/gain
resistor
2
DIN
Serial data input
3
CLR
Clear. Asynchronously sets
DAC register to 000hex.
PIN
1
4
SCLK
Serial clock input
5
CS
Chip select, active low
6
DOUT
Serial data output for
daisy-chaining
7
DGND
Digital ground
2
3
8
AGND
Analog ground
9
REFIN
Reference input
4
5
6
REFOUT
Reference output,
2.048V
11
V
SS
Negative power supply
12
7
VOUT
DAC output
13
8
V
DD
Positive power supply
14
RFB
Feedback resistor
MAX531
MAX538/
MAX539
NAME
____________________Pin Desc ription
_______________Detailed Desc ription
General DAC Disc ussion
The MAX531/MAX538/MAX539 use an “inverted” R-2R
ladder network with a single-supply CMOS op amp to con-
vert 12-bit digital data to analog voltage levels (see
Functional Diagram) The term “inverted” describes the
ladder network because the REFIN pin in current-output
DACs is the summing junction, or virtual ground, of an op
amp. However, such use would result in the output volt-
age being the inverse of the reference voltage. The
MAX531/MAX538/MAX539’s topology makes the output
the same polarity as the reference input.
An internal reset circuit forces the DAC register to reset to
000hex on power-up. Additionally, a clear CLR pin, when
held low, sets the DAC register to 000hex. CLR operates
asynchronously and independently from the chip select
CS pin.
Buffer Amplifier
The output buffer is a unity-gain stable, rail-to-rail output,
BiCMOS op amp. Input offset voltage and CMRR are
trimmed to achieve better than 12-bit performance.
Settling time is 25μs to 0.01% of final value. The output is
short-circuit protected and can drive a 2k
load with more
than 100pF load capacitance.
t
CSH0
t
CSS
t
CH
t
CL
t
CSH1
t
CSW
t
DS
t
DH
t
DO
CS
SCLK
DIN
DOUT
t
CS1
Figure 1. Timing Diagram
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