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參數(shù)資料
| 型號： | MAX5316GTG+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 11/33頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT SPI 24TQFN |
| 產(chǎn)品培訓(xùn)模塊： | Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 設(shè)置時間： | 3µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 功率耗散（最大）： | 2.29W |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 24-TQFN-EP（4x5） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
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19
MAX5316
16-Bit, ±1 LSB Accuracy Voltage Output
DAC with SPI Interface
Pin Description (continued)
PIN
NAME
FUNCTION
5
DIN
SPI Bus Serial Data Input. See the Serial Interface section for details.
6
SCLK
SPI Bus Serial Clock Input. See the Serial Interface section for details.
7
CS
SPI Bus Active-Low Chip-Select Input. See the Serial Interface section for details.
8
TC/SB
DIN Format Select Input. Connect TC/SB to DGND to set the data input format to straight binary or to
VDDIO to set it to two’s complement.
9
PD
Active-High Power-Down Input. Connect PD to DGND for normal operation. Connect PD to VDDIO to
place the device in power-down. In power-down, OUT (analog voltage output) is connected to AGND
through a 2kω resistor, but the contents of the input registers and the DAC latch do not change. The SPI
interface remains active in power-down.
10
AVSS
Negative Analog Power-Supply Input. Connect to AGND or a negative supply voltage. When connected to
the negative supply voltage, bypass AVSS with a 0.1F capacitor to AGND.
11
AGND
Analog Ground. Connect to the analog ground plane.
12, 19
AVDD1
Positive Analog Power-Supply Input. Bypass each AVDD_ locally with a 0.1F and 10F capacitor to
AGND (analog ground plane). Connect AVDD1 and AVDD2 together.
13
OUT
Buffered Analog Voltage Output. Connect OUT to RFB externally to close the output buffer feedback loop.
The buffered output is capable of directly driving a 10kω load. The state of M/Z sets the power-on reset
state of OUT (zero or midscale). In power-down, OUT is connected to AGND through a 2kω pulldown
resistor.
14
RFB
Feedback Resistor Input. RFB is connected through the internal feedback resistor to the inverting input of
the analog output buffer. Externally connect RFB to OUT to close the output buffer feedback loop.
15
REFO
Voltage Reference Buffered Output. Bypass with a 100pF capacitor to AGND.
16
REF
High-Impedance 10Mω Voltage Reference Input
17
AGND_S
DAC Analog Ground Sense
18
AGND_F
DAC Analog Ground Force. Connect to the analog ground plane.
19
AVDD2
Positive Analog Power-Supply Input. AVDD2 supplies power to the internal digital linear regulator. Bypass
AVDD2 locally to AGND with 0.1F and 10F capacitors. Connect AVDD2 and AVDD1 together.
20
BYPASS
Internal Bypass Connection. Connect BYPASS to DGND with 0.01F and 1F capacitors.
21
DGND
Digital Ground
22
VDDIO
Digital Interface Power-Supply Input. Connect to a 1.7V to 5.5V logic-level supply. Bypass VDDIO with a
0.1F capacitor to DGND. The supply voltage at VDDIO sets the logic-level for the digital interface.
23
RST
Active-Low Reset Input. Drive RST low to DGND to put the device into a reset state. A reset state sets all
SPI input registers to their default power-on reset states as defined by the state of inputs M/Z and TC/SB.
Set RST high to VDDIO, the DAC output remains at the state defined by M/Z until LDAC is taken low.
24
READY
SPI Active-Low Ready Output. READY asserts low when the device successfully completes processing an
SPI data frame. READY asserts high at the next rising edge of CS. In daisy-chain applications, the READY
output typically drives the CS input of the next device in the chain or a GPIO of a microcontroller.
—
EP
Exposed Pad. EP is internally connected to AGND. Connect to the analog ground plane.
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