參數(shù)資料
型號: MAX5316GTG+
廠商: Maxim Integrated Products
文件頁數(shù): 24/33頁
文件大?。?/td> 0K
描述: IC DAC 16BIT SPI 24TQFN
產(chǎn)品培訓模塊: Obsolescence Mitigation Program
標準包裝: 60
設置時間: 3µs
位數(shù): 16
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字,雙 ±
功率耗散(最大): 2.29W
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤
供應商設備封裝: 24-TQFN-EP(4x5)
包裝: 管件
輸出數(shù)目和類型: 1 電壓,單極;1 電壓,雙極
30
MAX5316
16-Bit, ±1 LSB Accuracy Voltage Output
DAC with SPI Interface
shielding to improve noise immunity. Do not run analog
and digital signals parallel to one another (especially
clock signals) and avoid routing digital lines underneath
the device package. Connect the exposed pad to AGND
(analog ground plane).
For a recommended layout, consult the MAX5316/
MAX5318 Evaluation Kit datasheet.
Voltage Reference Selection and Layout
The voltage reference should be placed close to the DAC.
The same power-supply decoupling and grounding rules
as the DAC should be implemented. Many voltage refer-
ences require an output capacitor for stability or noise
reduction. Provided the trace between the reference
device and the DAC is kept short and well shielded, a sin-
gle capacitor may be used and placed close to the DAC.
However, for improved noise immunity, additional capaci-
tors may be used but be careful not to exceed the recom-
mended capacitance range for the voltage reference.
Refer to Applications Note AN4300: Calculating the Error
Budget in Precision Digital-to-Analog Converter (DAC)
Applications for detailed description of voltage refer-
ence parameters and trading off the error budget. The
MAX6126 is recommended for 16-bit applications.
Optimizing Data Throughput Rate
The LDAC and BUSY Interaction section details the timing
of data written to the device and how the DAC is updated.
Data throughput speed can be increased by overlapping
the data load time with the busy period and settling time
as shown below in Figure 10. Following the 24th SCLK
falling edge, the device holds BUSY low while transfer-
ring the value from the DIN register to the DAC register.
Providing that the LDAC falling edge arrives before the
24th SCLK falling edge, and assuming the SPI clock fre-
quency is high enough, the throughput period is therefore
limited by tBUSY and settling times only. A slight further
increase in throughput time can be gained by either tog-
gling LDAC during the busy period or by pulling it low
permanently. However, the exact point at which the DAC
update occurs is then determined internally as indicated
by the BUSY line rising edge. This is not an exact time.
BUSY Line Pullup Resistor Selection
The BUSY pin is an open-drain output. It therefore
requires a pullup resistor. A 5.1kI value is recommend-
ed as a compromise between power and speed. Stray
capacitance on this line can easily slow the rise time
to an unacceptable level. The BUSY pin can sink up to
5mA. Therefore a resistor as low as VDDIO/0.005 may be
used if faster rise times are required.
Figure 10. Optimum Throughput with Stable Update Period
24TH SCLK
tBUSY
DIN
OUT
BUSY
LDAC
24TH SCLK
LDAC FALLING EDGE BEFORE 24TH SCLK FALLING EDGE
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