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參數(shù)資料
| 型號： | MAX5312EAE |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | DAC |
| 英文描述： | +-10V, 12-Bit, Serial, Voltage-Output DAC |
| 中文描述： | SERIAL INPUT LOADING, 10 us SETTLING TIME, 12-BIT DAC, PDSO16 |
| 封裝： | 5.30 MM, MO-150, SSOP-16 |
| 文件頁數(shù)： | 14/19頁 |
| 文件大?。?/td> | 1086K |
| 代理商： | MAX5312EAE |
M
Data in the shift register is transferred to the input register
during the appropriate software command only. Data in
the input register is transferred to the DAC register in one
of two ways: using the software command, or through
external logic control using the asynchronous load input
(
LDAC
). Table 2 shows the software commands that
transfer the data from the shift register to the input and/or
DAC registers. The
CLR
, an external logic control, asyn-
chronously forces the input and DAC registers to zero
code, and the output to 0V, in both unipolar and bipolar
modes. The interface timing is shown in Figures 2 and 3.
Wait a minimum of 100ns after
CS
goes high before
implementing
LDAC
or
CLR
. If either of these logic
inputs activates during a data transfer, the incoming
data is corrupted and needs to be reloaded. For soft-
ware control only, connect
LDAC
and
CLR
high.
DAC Architecture
The MAX5312 uses an inverted DAC ladder architec-
ture to convert the digital input into an analog output
voltage. The digital input controls weighted-switches
that connect the DAC ladder nodes to either REF or
GND (Figure 4). The sum of the weights produces the
analog equivalent of the digital-input word and is then
buffered at the output.
±10V, 12-Bit, Serial, Voltage-Output DAC
14
______________________________________________________________________________________
CONTROL BITS
DATA BITS
MSB
C3
LSB
D0
C2
C1
C0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
Table 1. Serial-Data Format
CONTROL BITS*
C3
C2
0
0
0
0
0
1
0
1
1
0
1
1
INPUT DATA
D11–D0
XXXXXXXXXXXX
12-bit DAC data
12-bit DAC data
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
C1
0
1
0
1
0
0
C0
0
0
0
0
0
0
FUNCTION
No operation; command is ignored.
Load input register from shift register; DAC output unchanged.
Load input and DAC registers from shift register; DAC output updated.
Load D AC r eg ster fr om i np ut r eg ster D AC outp ut up d ated i np ut r eg ster unchang ed
Enter shutdown; input and DAC registers unchanged.
Exit shutdown; input and DAC registers unchanged.
Table 2. Serial-Interface Programming Commands
X
= Don’t care.
*
All unlisted commands are reserved commands. Do not use.
SCLK
DIN
COMMAND EXECUTED
9
8
16
(1)
1
C2
C3
D0
C1
C0
D11
D10
D9
D6
D5
D4
D3
D2
D1
D8
D7
CS
Figure 2. Serial-Interface Signals
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