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參數(shù)資料
| 型號： | MAX5312EAE+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 8/19頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT 5V/10V SER 16-SSOP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 76 |
| 設置時間： | 10µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.209"，5.30mm 寬） |
| 供應商設備封裝： | 16-SSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | * |
| 產(chǎn)品目錄頁面： | 1397 (CN2011-ZH PDF) |
MAX5312
±10V, 12-Bit, Serial, Voltage-Output DAC
16
______________________________________________________________________________________
External Reference and Transfer
Functions
Connect an external 2V to 5.25V reference to REF (the
MAX6350 is recommended). Set the output voltage
range with the reference and the input code by using
the equations below.
Unipolar Output Voltage:
where
Bipolar Output Voltage:
where
where VOUT_UNI is the unipolar output voltage, VOUT_BIP
is the bipolar output voltage, LSBUNI is the unipolar LSB
step size, LSBBIP is the bipolar LSB step size, VREF is
the reference voltage, and CODE is the decimal equiva-
lent of the binary, 12-bit, DAC input code.
In either case, a 000hex input code produces the mini-
mum output (-2 x VREF for bipolar and 0 for unipolar),
an 800hex input code produces the midscale output (0
for bipolar and VREF for unipolar), and a FFFhex input
code produces the full-scale output (2 x VREF for bipo-
lar and unipolar).
Output Amplifiers
The output-amplifier section can be configured as
either unipolar or bipolar by the UNI/BIP logic input.
With UNI/BIP forced low, SW1 and SW2 in Figure 4 are
closed, and SW3 is open. This configuration channels
the DAC output through two output stages to generate
the ±2 x VREF output swing. The first amplifier gener-
ates the ±VREF voltage range and the second amplifier
increases it by two. When configured for bipolar opera-
tion, the MAX5312 must be driven with dual ±12V to
±15V power supplies.
With UNI/BIP forced high, switches SW1 and SW2 are
open, and SW3 is closed. This configuration channels
the DAC output through only a single gain stage to gen-
erate a 0 to (2 x VREF) output swing.
Daisy Chaining
SPI-/QSPI-/MICROWIRE-compatible devices can be
daisy chained to reduce I/O lines from the host con-
troller (Figure 7). Daisy chain devices by connecting
the DOUT of one device to the DIN of the next, and
connect the SCLK of all devices to a common clock.
Data is shifted out of DOUT 16.5 clock cycles after it is
shifted into DIN, and is available on the rising edge of
the 17th clock cycle. The SPI-/QSPI-/MICROWIRE-com-
patible serial interface normally works at up to 10MHz,
but must be slowed to 6.0MHz if daisy chaining. DOUT
is high impedance when CS is high.
Shutdown
Shutdown is controlled by software commands or by the
SHDN logic input. The SHDN logic input can be imple-
mented at any time. The SPI-/QSPI-/MICROWIRE-compat-
ible serial interface remains fully functional, and the device
is programmable while shut down. When shut down, the
MAX5312 supply current reduces to 3.5A, DOUT is high
impedance, and OUT is pulled to SGND through the inter-
nal feedback resistors of the output amplifier (Figure 1).
When coming out of shutdown, or during device power-
up, allow 350s for the output to stabilize.
LSB
V
BIP
REF
=
×
4
2
12
V
LSB
CODE
V
OUT BIP
BIP
REF
_
(
) (
)
=×
×
2
LSB
V
UNI
REF
= ×
2
12
V
LSB
CODE
OUT UNI
UNI
_
=×
BINARY DAC CODE
ANALOG OUTPUT
MSB
LSB
UNIPOLAR (UNI/
BIP_ = HIGH)
BIPOLAR (UNI/
BIP_ = LOW)
1111 1111 1111
+2 x VREF (4095 / 4096)
+2 x VREF (2047 / 2048)
1000 0000 0001
+2 x VREF (2049 / 4096)
+2 x VREF (1 / 2048)
1000 0000 0000
+2 x VREF (2048 / 4096) = VREF
0
0111 1111 1111
+2 x VREF (2047 / 4096)
-2 x VREF (1 / 2048)
0000 0000 0001
+2 x VREF (1 / 4096)
-2 x VREF (2047 / 2048)
0000 0000 0000
0
-2 x VREF (2048 / 2048) = -2 x VREF
Table 3. Output Voltage as Input Code Examples
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