參數(shù)資料
型號: MAX5294EUD
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: DAC
英文描述: Low Power 5V RS232 Dual Driver/Receiver with 0.1?μF Capacitors; Package: SO; No of Pins: 16; Temperature Range: -40?°C to 85?°C
中文描述: SERIAL INPUT LOADING, 2 us SETTLING TIME, 8-BIT DAC, PDSO14
封裝: 6.50 X 5 MM, MO-153AB-1, TSSOP-14
文件頁數(shù): 26/33頁
文件大?。?/td> 941K
代理商: MAX5294EUD
M
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
26
______________________________________________________________________________________
SET
,
MID
,
CLR
The
SET
,
MID
, and
CLR
signals force the DAC outputs
to full scale, midscale, or zero scale (Figure 5). These
signals cannot be active at the same time.
The active-low
SET
input forces the DAC outputs to full
scale when
SET
is low. When
SET
is high, the DAC out-
puts follow the data in the DAC registers.
The active-low
MID
input forces the DAC outputs to mid-
scale when
MID
is low. When
MID
is high, the DAC out-
puts follow the data in the DAC registers.
The active-low
CLR
input forces the DAC outputs to zero
scale when
CLR
is low. When
CLR
is high, the DAC out-
puts follow the data in the DAC registers.
If
CLR
,
MID
, or
SET
signals go low in the middle of a write
command, reload the data to ensure accurate results.
Power-Down Lockout (
PDL
)
The
PDL
active-low software-shutdown lockout input
overrides (not overwrites), the PD_0 and PD_1 shut-
down mode bits.
PDL
cannot be active at the same
time as
SHDN1K
or
SHDN100K
(see the
Shutdown
Mode (
SHDN1K
,
SHDN100K
)
section).
If the PD_0 and PD_1 bits command the DAC to shut
down prior to
PDL
going low, the DAC returns to shut-
down mode immediately after
PDL
goes high, unless
the PD_0 and PD_1 bits are changed in the meantime.
Shutdown Mode (
SHDN1K
,
SHDN100K
)
The
SHDN1K
and
SHDN100K
are active-low signals
that override (not overwrite) the PD_1 and PD_0 bit set-
tings. For the MAX5290/MAX5292/MAX5294, drive
SHDN1K
low to select shutdown mode with OUTA and
OUTB internally terminated with 1k
to ground, or drive
SHDN100K
low to select shutdown with an internal
100k
termination. For the MAX5291/MAX5293/
MAX5295, drive
SHDN1K
low for shutdown with 1k
output termination, or drive
SHDN100K
low for shut-
down with high-impedance outputs.
Data Output (DOUTRB, DOUTDC0, DOUTDC1)
UPIO1 and UPIO2 can be configured as serial data
outputs, DOUTRB (data out for read back), DOUTDC0
(data out for daisy-chaining, mode 0), and DOUTDC1
(data out for daisy-chaining, mode 1). The differences
between DOUTRB and DOUTDC0 (or DOUTDC1) are
as follows:
The source of read-back data on DOUTRB is the
DOUT register. Daisy-chain DOUTDC_ data comes
directly from the shift register.
Read-back data on DOUTRB is only present after a
DAC read command. Daisy-chain data is present on
DOUTDC_ for any DAC write after the first 16 bits
are written.
The DOUTRB idle state (
CS
= high) for read back is
high impedance. Daisy-chain DOUTDC_ idles high
when inactive to avoid floating the data input in the
next device in the daisy-chain.
See Figures 1 and 2 for timing details.
t
CMS
t
LDL
t
S
±
0.5 LSB
TOGG
V
OUT_
LDAC
PDL
CLR,
MID, OR
SET
PDL AFFECTS DAC OUPTUTS (V
OUT_
) ONLY IF DACS WERE PREVIOUSLY SHUT DOWN.
Figure 5. Asynchronous Signal Timing
t
GP
t
LDS
END OF
CYCLE*
GPO_
LDAC
*END-OF-CYCLE REPRESENTS THE RISING EDGE OF CS OR THE 16TH
ACTIVE CLOCK EDGE, DEPENDING ON THE MODE OF OPERATION.
Figure 6. GPO_ and
LDAC
Signal Timing
相關(guān)PDF資料
PDF描述
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