參數(shù)資料
型號(hào): MAX5291AEUE
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: DAC
英文描述: Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs
中文描述: SERIAL INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, PDSO16
封裝: 6.50 X 5 MM, MO-153AB, TSSOP-16
文件頁數(shù): 9/33頁
文件大小: 941K
代理商: MAX5291AEUE
M
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
_______________________________________________________________________________________
9
TIMING CHARACTERISTICS
DSP Mode Enabled (1.8V Logic) (Figure 2) (continued)
(DVDD= 1.8V to 3.6V, DGND = 0, TA= TMINto TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
UPIO_ TIMING CHARACTERISTICS
DOUT Tri-State Time when
Exiting DOUTDC0, DOUTDC1, or
DOUTRB UPIO_ Modes
t
DOZ
C
L
= 20pF, from end of write cycle to UPIO_
in high impedance
200
ns
DOUTRB Tri-State Time from
CS
Rise
t
DRBZ
C
L
= 20pF, from rising edge of
CS
to UPIO_
in high impedance
40
ns
DOUTRB Tri-State Enable Time
from 8th SCLK Fall
t
ZEN
C
L
= 20pF, from 8th falling edge of SCLK to
UPIO_ driven out of tri-state
40
ns
LDAC
Pulse-Width Low
LDAC
Effective Delay
CLR
,
MID
,
SET
Pulse-Width Low
GPO Output Settling Time
t
LDL
t
LDS
t
CMS
t
GP
Figure 5
Figure 6
Figure 5
Figure 6
40
200
40
ns
ns
ns
ns
200
GPO Output High-Impedance
Time
t
GPZ
200
ns
Note 1:
For the force-sense versions, FB_ is connected to its respective OUT_. VOUT(max) = VREF / 2, unless otherwise noted.
Note 2:
Linearity guaranteed from decimal code 82 to 4095 for the MAX5290B/MAX5291B (12-bit, B-grade), code 21 to 1023 for the
MAX5292/MAX5293 (10-bit), and code 5 to 255 for the MAX5294/MAX5295 (8-bit).
Note 3:
DAC-to-DAC crosstalk is measured as follows: outputs of DACA and DACB are set to full scale and the output of DACB is
measured. While keeping DACB unchanged, the output of DACA is transitioned to zero scale and the
VOUTof DACB is
measured. The procedure is repeated with DACA and DACB interchanged. DAC-to-DAC crosstalk is the maximum
VOUT
measured.
Note 4:
Represents the functional range. The linearity is guaranteed at VREF= 2.5V. See the
Typical Operating Characteristics
sec-
tion for linearity at other voltages.
Note 5:
Guaranteed by design.
Note 6:
The reference -3dB bandwidth is measured with a 0.1VP-Psine wave on VREFand with the input code at full scale.
Note 7:
In some daisy-chain modes, data is required to be clocked in on one clock edge and the shifted data clocked out on the fol-
lowing edge. In the case of a 1/2 clock-period delay, it is necessary to increase the minimum high/low clock times to 25ns
(2.7V) or 50ns (1.8V).
Note 8:
The falling edge of
DSP
starts a DSP-type bus cycle, provided that
CS
is also active low to select the device.
DSP
active low
and
CS
active low must overlap by a minimum of 10ns (2.7V) or 20ns (1.8V).
CS
can be permanently low in this mode of
operation.
相關(guān)PDF資料
PDF描述
MAX5290AEUD Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs
MAX5290BEUD Low Power 5V RS232 Dual Driver/Receiver with 0.1?μF Capacitors; Package: SO; No of Pins: 16; Temperature Range: -40?°C to 85?°C
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