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參數(shù)資料
| 型號(hào)： | MAX5230 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | 3V/5V, 12-Bit, Serial Voltage-Output Dual DACs with Internal Reference |
| 中文描述： | 3V/5V、12位、串行電壓輸出、雙路DAC，內(nèi)置電壓基準(zhǔn) |
| 文件頁(yè)數(shù)： | 13/18頁(yè) |
| 文件大?。?/td> | 974K |
| 代理商： | MAX5230 |
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Power-Down and Shutdown Modes
As described in Tables 2 and 3, several serial interface
commands put one or both of the DACs into shutdown
mode. Shutdown modes are completely independent
for each DAC. In shutdown, the amplifier output be-
comes high impedance, and OUT_ terminates to OS_
through the 200k
(typ) gain resistors. Optionally (see
Tables 2 and 3), OUT_ can have an additional termina-
tion of 1k
to AGND.
Full power-down mode shuts down the main bias gene-
rator, reference, and both DACs. The shutdown impe-
dance of the DAC outputs can still be controlled
independently, as described in Tables 2 and 3.
A serial interface command exits shutdown mode and
updates a DAC register. Each DAC can exit shutdown
at the same time or independently (see Tables 2 and
3). For example, if both DACs are shut down, updating
the DAC A register causes DAC A to power up, while
DAC B remains shut down. In full power-down mode,
powering up either DAC also powers up the main bias
generator and reference. To change from full power-
down to both DACs shutdown requires the waking of at
least one DAC between states.
When powering up the MAX5230/MAX5231 (powering
V
DD
), allow 400μs (max) for the output to stabilize. When
exiting full power-down mode, also allow 400μs (max) for
the output to stabilize. When exiting DAC shutdown
mode, allow 160μs (max) for the output to stabilize.
Reset Value (RSTV) and
Clear (
CLR
) Inputs
Driving
CLR
low asynchronously forces both DAC out-
puts and all the internal registers (input registers and
DAC registers) for both DACs to either zero or midscale,
depending on the level at RSTV. RSTV = DGND sets the
zero value, and RSTV, = V
DD
sets the midscale value.
The internal power-on reset circuit sets the DAC out-
puts and internal registers to either zero or midscale
when power is first applied to the device, depending on
the level at RSTV as described in the preceding para-
graph. The DAC outputs are enabled after power is first
applied. In order to obtain the midscale value on
power-up (RSTV = V
DD
), the voltage on RSTV must rise
simultaneously with the V
DD
supply.
Load DAC Input (
LDAC
)
Asserting
LDAC
asynchronously loads the DAC registers
from their corresponding input registers (DACs that are
shut down remain shut down). The
LDAC
input is totally
asynchronous and does not require any activity on
CS
,
SCLK, or DIN in order to take effect. If
LDAC
is asserted
coincident with a rising edge of
CS,
which executes a
serial command modifying the value of either DAC input
register, then
LDAC
must remain asserted for at least
30ns following the
CS
rising edge. This requirement
applies only for serial commands that modify the value of
the DAC input registers.
Power-Down Lockout Input (
PDL
)
Driving
PDL
low disables shutdown of either DAC. When
PDL
is low, serial commands to shut down either DAC are
ignored. When either DAC is in shutdown mode, a high-
to-low transition on
PDL
brings the DACs and the refer-
ence out of shutdown with DAC outputs set to the state
prior to shutdown.
M
3V/5V, 12-Bit, Serial Voltage-Output Dual DACs
with Internal Reference
______________________________________________________________________________________
13
Table 3. P1 Shutdown Modes
P1 (A/B)
0
1
SHUTDOWN MODE
Shut down with internal 1k
load to GND
Shut down with internal 200k
load to GND
SCLK
DIN
CS
MOSI
SCK
5V
I/O
SPI/QSPI
PORT
SS
MAX5230
MAX5231
Figure 4. SPI/QSPI Interface Connections
SCLK
DIN
CS
SK
SO
I/O
MICROWIRE
PORT
MAX5230
MAX5231
Figure 5. Connections for MICROWIRE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX5230-MAX5231 | 3V/5V, 12-Bit, Serial Voltage-Output Dual DACs with Internal Reference |
| MAX5230AEEE | 3V/5V, 12-Bit, Serial Voltage-Output Dual DACs with Internal Reference |
| MAX5230BEEE | 3V/5V, 12-Bit, Serial Voltage-Output Dual DACs with Internal Reference |
| MAX5231 | 3V/5V, 12-Bit, Serial Voltage-Output Dual DACs with Internal Reference |
| MAX5231AEEE | 3V/5V, 12-Bit, Serial Voltage-Output Dual DACs with Internal Reference |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX5230AEEE | 功能描述:數(shù)模轉(zhuǎn)換器- DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX5230AEEE+ | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 12-Bit 2Ch Precision DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX5230AEEE+T | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 12-Bit 2Ch Precision DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX5230AEEE-T | 功能描述:數(shù)模轉(zhuǎn)換器- DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX5230BEEE | 功能描述:數(shù)模轉(zhuǎn)換器- DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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