• 參數(shù)資料
    型號(hào): MAX5200BEUB
    廠(chǎng)商: MAXIM INTEGRATED PRODUCTS INC
    元件分類(lèi): DAC
    英文描述: CONNECTOR
    中文描述: SERIAL INPUT LOADING, 25 us SETTLING TIME, 16-BIT DAC, PDSO10
    封裝: 5 X 3 MM, MICRO, SOP-10
    文件頁(yè)數(shù): 9/13頁(yè)
    文件大?。?/td> 288K
    代理商: MAX5200BEUB
    M
    Low-Cost, Voltage-Output, 16-Bit DACs with
    Internal Reference in μMAX
    _______________________________________________________________________________________
    9
    data loading at the data input (DIN). Pull
    CS
    low and
    clock in each bit of the 16-bit digital word on the rising
    edge of the serial clock (SCLK). Two 8-bit bytes can be
    used, and do not require any additional time between
    them. Pulling
    CS
    high after loading the 16-bit word
    transfers that code into the DAC register and then
    updates the output. If
    CS
    is not kept low during the
    entire loading of the 16-bit word, data is corrupted. In
    this case, a new 16-bit word must be loaded.
    LDAC
    must be kept low at all times for the above instructions.
    An alternate method of interfacing and updating the
    MAX5200–MAX5203 can be done with a fourth digital
    input, the active-low load DAC (
    LDAC
    ).
    LDAC
    allows
    the output to update asynchronously after
    CS
    goes
    high. It is useful when updating multiple MAX5200–
    MAX5203s synchronously when sharing a single
    LDAC
    and
    CS
    line.
    LDAC
    must be kept high at all times dur-
    ing the data-loading sequence and must only be
    asserted when
    CS
    is high. Asserting
    LDAC
    when
    CS
    is
    low can cause corrupted data. To operate the
    MAX5200–MAX5203 using
    LDAC
    , pull
    LDAC
    high, pull
    CS
    low, load the 16-bit word as described in the previ-
    ous paragraph, and pull
    CS
    high again. Following these
    commands, the DAC output only updates when
    LDAC
    is asserted low (Figure 3).
    Shutdown Mode
    The low-power shutdown mode reduces supply current
    to typically 1μA and a maximum of 10μA. Shutdown
    mode is not activated through command words, as is
    common among D/A converters. These devices require
    careful manipulation of
    CS
    and SCLK (Figure 4).
    Shutting Down
    To shut down the MAX5200–MAX5203, change the
    state of SCLK (either a high to low or low to high transi-
    tion can be used) and pulse two falling
    CS
    edges. In
    order to keep the device in shutdown mode, SCLK
    must
    not change state. SCLK must remain in the state
    it is in after the two
    CS
    pulses.
    Waking Up
    There are two methods to wake up the MAX5200–
    MAX5203. Pulse one falling
    CS
    edge or transition SCLK.
    It takes 50μs typically from the
    CS
    falling edge or SCLK
    transition for the DAC to return to normal operation.
    Power-On Reset
    The MAX5200–MAX5203 have a power-on reset circuit to
    set the DAC’s output to a known state when V
    DD
    is first
    applied. The MAX5200/MAX5202 reset to midscale (code
    8000 hex) upon power-up. The MAX5201/MAX5203 reset
    to zero scale (code 0000 hex) upon power-up. This
    ensures that unwanted output voltages do not occur
    immediately following a system power-up, such as a loss
    of power. It is required to apply V
    DD
    first before any other
    inputs (DIN, SCLK,
    CLR
    ,
    LDAC
    , and
    CS
    ).
    t
    CL
    t
    CH
    t
    CSS
    D14
    D15
    t
    DS
    t
    DH
    D0
    t
    CSH
    t
    CS1
    t
    CS0
    SCLK
    CS
    DIN
    t
    CP
    t
    CSWH
    NOTE:
    LDAC IS LOGIC LOW.
    Figure 2. 3-Wire Interface Timing Diagram
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