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    參數(shù)資料
    型號(hào): MAX5158EEE
    廠商: MAXIM INTEGRATED PRODUCTS INC
    元件分類(lèi): DAC
    英文描述: Low-Power, Dual, 10-Bit, Voltage-Output DACs with Serial Interface
    中文描述: DUAL, SERIAL INPUT LOADING, 16 us SETTLING TIME, 10-BIT DAC, PDSO16
    封裝: 0.150 INCH, 0.025 INCH PITCH, QSOP-16
    文件頁(yè)數(shù): 13/16頁(yè)
    文件大小: 181K
    代理商: MAX5158EEE
    Serial-Data Output
    The serial-data output, DOUT, is the internal shift regis-
    ter’s output. DOUT allows for daisy chaining of devices
    and data readback. The MAX5158/MAX5159 can be
    programmed to shift data out of DOUT on SCLK’s
    falling edge (Mode 0) or on the rising edge (Mode 1).
    Mode 0 provides a lag of 16 clock cycles, which main-
    tains compatibility with SPI/QSPI and Microwire inter-
    faces. In Mode 1, the output data lags 15.5 clock
    cycles. On power-up, the device defaults to Mode 0.
    User-Programmable Logic Output (UPO)
    UPO allows an external device to be controlled through
    the serial interface (Table 1), thereby reducing the num-
    ber of microcontroller I/O pins required. On power-up,
    UPO is low.
    Power-Down Lockout Input (
    PDL
    )
    The power-down lockout pin (
    PDL
    ) disables software
    shutdown when low. When in shutdown, transitioning
    PDL
    from high to low wakes up the part with the output
    set to the state prior to shutdown.
    PDL
    can also be
    used to asynchronously wake up the device.
    Daisy Chaining Devices
    Any number of MAX5158/MAX5159s can be daisy
    chained by connecting the DOUT pin of one device to
    the DIN pin of the following device in the chain (Figure 7).
    Since the MAX5158/MAX5159’s DOUT pin has an internal
    active pull-up, the DOUT sink/source capability deter-
    mines the time required to discharge/charge a capacitive
    load. Refer to the digital output V
    OH
    and V
    OL
    specifica-
    tions in the Electrical Characteristics.
    Figure 8 shows an alternate method of connecting sev-
    eral MAX5158/MAX5159s. In this configuration, the
    data bus is common to all devices; data is not shifted
    through a daisy chain. More I/O lines are required in
    this configuration because a dedicated chip-select
    input (
    CS
    ) is required for each IC.
    __________Applic ations Information
    Unipolar Output
    Figure 9 shows the MAX5158/MAX5159 configured for
    unipolar, rail-to-rail operation with a gain of +2V/V. The
    MAX5158 can produce a 0V to 4.096V output with a
    2.048V reference (Figure 9), while the MAX5159 can
    M
    Low-Power, Dual, 10-Bit, Voltage-Output DACs
    with S erial Interfac e
    Table 2. Unipolar Code Table (Gain = +2)
    MAX5158
    MAX5159
    DAC_
    GAIN = +2V/V
    REF_
    OUT_
    OS_
    DGND
    AGND
    +5V/+3V
    V
    DD
    R
    R
    Figure 9. Unipolar Output Circuit (Rail-to-Rail)
    MAX5158
    MAX5159
    DAC _
    AGND
    DGND
    REF_
    OUT_
    OS_
    V
    OS
    +5V/+3V
    V
    DD
    R
    R
    ______________________________________________________________________________________
    13
    ANALOG OUTPUT
    11
    1111
    1111 (000)
    10
    0000
    0001 (000)
    DAC CONTENTS
    MSB
    LSB
    10
    0000
    0000 (000)
    01
    1111
    1111 (000)
    00
    0000
    0000 (000)
    0V
    00
    0000
    0001 (000)
    +V
    1023
    1024
    x 2
    REF
    +V
    513
    1024
    x 2
    REF
    +V
    512
    1024
    x 2
    V
    REF
    REF
    =
    +V
    511
    1024
    x 2
    REF
    +V
    1
    1024
    REF
    Figure 10. Setting OS_ for Output Offset
    Note:
    ( ) are for the sub bits.
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