參數(shù)資料
型號: MAX5115EEP
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: DAC
英文描述: Nonvolatile, Quad, 8-Bit DACs with 2-Wire Serial Interface
中文描述: SERIAL INPUT LOADING, 8 us SETTLING TIME, 8-BIT DAC, PDSO20
封裝: 0.150 INCH, 0.025 INCH PITCH, MO-137AD, QSOP-20
文件頁數(shù): 14/19頁
文件大小: 459K
代理商: MAX5115EEP
M
Nonvolatile, Quad, 8-Bit DACs with 2-Wire Serial
Interface
14
______________________________________________________________________________________
Write Cycle
The write command requires 27 clock cycles. In write
mode (R/
W
= 0), the command byte that follows the
address byte controls the MAX5115/MAX5116 (Table 1).
For a write function, set bits C7 and C6 to zero. Set bits
C5 and C4 to select the volatile or nonvolatile register
(Table 2). Set bits C3–C0 to select the respective DAC
register (Table 3). The registers update on the rising
edge of the 26th SCL pulse. Prematurely aborting the
write cycle does not update the DAC. See Table 4 for a
summary of the write commands.
Read Cycle
A read command requires 36 clock cycles. In read
mode, the MAX5115/MAX5116 send the contents of the
volatile and nonvolatile registers to the bus. Reading a
register requires a REPEATED START (Sr) condition. To
read a register first, write a read command (R/
W
= 0,
Figure 9). Set the most significant 2 bits of the com-
mand byte to 10 (C7 = 1 and C6 = 0). Set bits C5 and
C4 to read from either the volatile or nonvolatile register
(Table 5). Set bits C3–C0 to select the desired DAC
register (Table 6). After the command byte, send a (Sr)
condition followed by the address of the device
(R/
W
= 1). The MAX5115/MAX5116 then acknowledge
and send the data on the bus.
Mute/Power-Down Mode
The MAX5115/MAX5116 feature software-controlled
mute and power-down modes for each DAC. The
power-down mode places the DAC output in a high-
impedance state and reduces quiescent-current con-
sumption (25μA (max) with all DACs powered-down).
S
0
1
0
A3
A2
A1
A0
A3
A2
A1
A0
1
0
NV
V
R3
R2
R1
R0
C7
C6
C5
C4
C3
C2
C1
C0
Sr
0
1
0
MSB
LSB
MSB
LSB
LSB
MSB
ACK
ACK
ACK
NACK
R/W
= 1
D7
D6
D5
D4
D3
D2
D1
D0
P
MSB
LSB
ADDRESS AND COMMAND BYTES GENERATED BY MASTER DEVICE
DATA BYTE GENERATED BY MAX5115/MAX5116
NACK GENERATED BY
MASTER DEVICE
R/W
= 0
Figure 9. Example Read Word Data Sequence
ADDRESS BYTE
COMMAND BYTE
DATA BYTE
S
R/
W
C
7
C
7
C
6
C
6
C
5
N
V
C
4
C
3
R
3
C
2
R
2
C
1
R
1
C
0
R
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
STOP
Master
SDA
S
0 1 0
A
3
A
2
A
1
A
0
0
V
D7–D0
P
Slave
SDA
A
C
K
A
C
K
A
C
K
Table 1. Write Operation
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