device powers up (i.e." />
參數(shù)資料
型號(hào): MAX5102AEUE+T
廠商: Maxim Integrated Products
文件頁數(shù): 7/8頁
文件大?。?/td> 0K
描述: IC DAC 8BIT DUAL PAR-IN 16-TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
設(shè)置時(shí)間: 6µs
位數(shù): 8
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 2 電壓,單極
采樣率(每秒): *
input latches. To avoid output glitches in the MAX5102,
ensure that data is valid before WR goes low. When the
device powers up (i.e., VDD ramps up), all latches are
internally preset with code 00 hex.
Applications Information
External Reference
The reference source resistance must be considerably
less than the reference input resistance. To keep within
1LSB error in an 8-bit system, RS must be less than
RREF/256. Hence, maintain a value of RS < 1k
to
ensure 8-bit accuracy. If VREF is DC only, bypass REF
to GND with a 0.1F capacitor. Values greater than this
improve noise rejection.
Power Sequencing
The voltage applied to REF should not exceed VDD at
any time. If proper power sequencing is not possible,
connect an external Schottky diode between REF and
VDD to ensure compliance with the absolute maximum
ratings. Do not apply signals to the digital inputs before
the device is fully powered up.
Power-Supply Bypassing and
Ground Management
Digital or AC transient signals on GND can create noise
at the analog output. Return GND to the highest-quality
ground available. Bypass VDD with a 0.1F capacitor,
located as close to VDD and GND as possible.
Careful PC board ground layout minimizes crosstalk
between the DAC outputs and digital inputs.
Chip Information
TRANSISTOR COUNT: 6848
MAX5102
+2.7V to +5.5V, Low-Power, Dual, Parallel
8-Bit DAC with Rail-to-Rail Voltage Outputs
_______________________________________________________________________________________
7
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