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參數(shù)資料
| 型號： | MAX509-MAX510 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | RELAY |
| 中文描述： | 四，串行8位DAC與軌至軌輸出 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大小： | 235K |
| 代理商： | MAX509-MAX510 |
Serial Input Data Format and Control Codes
The 12-bit serial input format shown in Figure 3 com-
prises two DAC address bits (A1, A0), two control bits
(C1, C0) and eight bits of data (D0...D7).
The 4-bit address/control code configures the DAC as
shown in Table 1.
Load Input Register, DAC Registers Unchanged
(Single Update Operation)
When performing a single update operation, A1 and A0
select the respective input register. At the rising edge
of
CS
, the selected input register is loaded with the cur-
rent shift-register data. All DAC outputs remain
unchanged. This preloads individual data in the input
register without changing the DAC outputs.
Load Input and DAC Registers
This command directly loads the selected DAC register
at
CS
's rising edge. A1 and A0 set the DAC address.
Current shift-register data is placed in the selected
input and DAC registers.
For example, to load all four DAC registers simultaneously
with individual settings (DAC A = 1V, DAC B = 2V, DAC
C = 3V and DAC D = 4V), five commands are required.
First, perform four single input register update opera-
tions. Next, perform an “
LDAC
” command as a fifth
command. All DACs will be updated from their respec-
tive input registers at the rising edge of
CS
.
Update All DACs from Shift Registers
All four DAC registers are updated with shift-register
data. This command allows all DACs to be set to any
analog value within the reference range. This command
can be used to substitute
CLR
if code 00 hex is pro-
grammed, which clears all DACs.
No Operation (NOP)
The NOP command (no operation) allows data to be shift-
ed through the MAX509/MAX510 shift register without
affecting the input or DAC registers. This is useful in daisy
chaining (also see the Daisy-Chaining Devices section).
For this command, the data bits are "Don't Cares." As an
example, three MAX509/MAX510s are daisy-chained (A, B
and C), and DAC A and DAC C need to be updated. The
36-bit-wide command would consist of one 12-bit word for
device C, followed by an NOP instruction for device B and
a third 12-bit word with data for device A. At
CS
's rising
edge, only device B is not updated.
“LDAC” Command (Software)
All DAC registers are updated with the contents of their
respective input registers at
CS
's rising edge. With the
exception of using
CS
to execute, this performs the
same function as the asynchronous
LDAC
.
Set DOUT Phase – SCLK Rising (Mode 1, Default)
Mode 1 resets the serial output DOUT to transition at
SCLK's rising edge. This is the MAX509/MAX510’s
default setting after the supply voltage has been
applied.
The command also loads all DAC registers with the con-
tents of their respective input registers, and is identical to
the “
LDAC
” command.
M
Quad, S erial 8-Bit DACs
with Rail-to-Rail Outputs
______________________________________________________________________________________
11
This is the first bit shifted in
A101 076
G G G
D10
DIN
DOUT
Control and
Address bits
8-bit DAC data
MSB
LSB
Figure 3. Serial Input Format
(
LDAC
= H)
(
LDAC
= x)
(
LDAC
= x)
(
LDAC
= x)
(
LDAC
= x)
(
LDAC
= H)
1 0
1 1
x
x
x
x
x
x
x
x
D0
D1
D2
D3
D4
D5
D6
D7
C0
C1
A0
A1
8-Bit DAC Data
0 0
x 0
D0
D1
D2
D3
D4
D5
D6
D7
C0
C1
A0
A1
x
x
x
x
x
x
x
x
0 0
x 1
D0
D1
D2
D3
D4
D5
D6
D7
C0
C1
A0
A1
1 0
0 x
x
x
x
x
x
x
x
x
D0
D1
D2
D3
D4
D5
D6
D7
C0
C1
A0
A1
8-Bit Data
0 1
Address
D0
D1
D2
D3
D4
D5
D6
D7
C0
C1
A0
A1
8-Bit Data
1 1
Address
D0
D1
D2
D3
D4
D5
D6
D7
C0
C1
A0
A1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX510AEWE | Circular Connector; No. of Contacts:8; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:13; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:13-8 RoHS Compliant: No |
| MAX509BCAP | Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs |
| MAX509BEAP | Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs |
| MAX510BEPE | Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs |
| MAX509ACAP | Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX50A | 制造商:Datak Corporation 功能描述: |
| MAX50AB | 制造商:Datak Corporation 功能描述: |
| MAX-50M | 制造商:MDE 制造商全稱:MDE Semiconductor, Inc. 功能描述:HIGH CURRENT TRANSIENT VOLTAGE SUPPRESSOR |
| MAX510 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs |
| MAX5100 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:+2.7V to +5.5V, Low-Power, Quad, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs |
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