參數(shù)資料
型號(hào): MAX503ENG
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: DAC
英文描述: Low Power 5V RS232 Dual Driver/Receiver with 0.1?μF Capacitors; Package: SO; No of Pins: 16; Temperature Range: -40?°C to 85?°C
中文描述: PARALLEL, 8 BITS INPUT LOADING, 25 us SETTLING TIME, 10-BIT DAC, PDIP24
封裝: 0.300 INCH, PLASTIC, DIP-24
文件頁數(shù): 11/16頁
文件大小: 118K
代理商: MAX503ENG
M
5V, Low-Power, Parallel-Input,
Voltage-Output, 10-Bit DAC
______________________________________________________________________________________
11
V
IH
V
IL
DATA BITS
(8-BIT BYTE
OR 4-BIT NIBBLE)
A0–A1
V
IL
V
IH
ADDRESS BUS VALID
t
AWH
t
CWS
t
WR
t
CWH
t
AWS
t
DS
t
DH
DATA BUS
VALID
NOTE:
TIMING MEASUREMENT REFERENCE LEVEL IS V
IH +
V
IL
2
t
CLR
CS
WR
CLR
LDAC
t
LDAC
Figure 4. MAX503 Write-Cycle Timing Diagram
A small error voltage is added to the reference output
by the reference current flowing through the N-channel
pull-down transistor. The switch’s on resistance should
be less than 5
. A typical reference current of 100μA
would add 0.5mV to REFOUT. Since the reference cur-
rent and on resistance increase with temperature, the
overall temperature coefficient will degrade slightly.
As data is loaded into the DAC and the output moves
above GND, the op-amp quiescent current increases to
its nominal value and the total operating current aver-
ages 250μA. Using dual supplies (±5V), the op amp is
fully biased continuously, and the V
DD
supply current is
more constant at 250μA. The V
SS
current is typically
150μA.
The MAX503 logic inputs are compatible with TTL and
CMOS logic levels. However, to achieve the lowest
power dissipation, drive the digital inputs with rail-to-rail
CMOS logic. With TTL logic levels, the power require-
ment increases by a factor of approximately 2.
Parallel Logic Interfac e
In order to provide hardware and software compatibility
with the 12-bit MAX530, the MAX503 employs a 12-bit
digital interface. As shown in Figure 3, there is actually
a 12-bit input latch, and therefore 12 bits of data should
be written. The two least significant bits (S1 and S0) are
sub-LSB, and must always be 0s. Designed to interface
with 4-bit, 8-bit, and 16-bit microprocessors (μPs), the
MAX503 uses 8 data pins and double-buffered logic
inputs to load data as 4 + 4 + 4 or 8 + 4. The 12-bit
DAC latch is updated simultaneously through the con-
trol signal LDAC. Signals A0, A1, WR, and CS select
which input latches to update. The 12-bit data is bro-
ken down into nibbles (NB); NBL is the enable signal
for the lowest 4 bits (S0, S1, D0, D1), NBM is the
enable for the middle 4 bits, and NBH is the enable for
the highest and most significant 4 bits. Table 2 lists the
address decoding scheme.
Refer to Figure 4 for the MAX503 write-cycle timing
diagram.
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