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M
Dual-Phase, Parallelable, Average Current-Mode
Controllers
24
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The allowable deviation of the output voltage during the
fast transient load dictates the output capacitance and
ESR. The output capacitors supply the load step until
the controller responds with a greater duty cycle. The
response time (t
RESPONSE
) depends on the closed-loop
bandwidth of the converter. The resistive drop across
the capacitor ESR and capacitor discharge causes a
voltage drop during a step load. Use a combination of
SP polymer and ceramic capacitors for better transient
load and ripple/noise performance.
Keep the maximum output voltage deviation less than
or equal to the adaptive voltage-positioning window
(
V
OUT
). Assume 50% contribution each from the out-
put capacitance discharge and the ESR drop. Use the
following equations to calculate the required ESR and
capacitance value:
where I
STEP
is the load step and t
RESPONSE
is the
response time of the controller. Controller response
time depends on the control-loop bandwidth.
Current Limit
The average current-mode control technique of the
MAX5038/MAX5041 accurately limits the maximum out-
put current per phase. The MAX5038/MAX5041 sense
the voltage across the sense resistor and limit the peak
inductor current (I
L-PK
) accordingly. The ON cycle ter-
minates when the current-sense voltage reaches 45mV
(min). Use the following equation to calculate maximum
current-sense resistor value:
where PD
R
is the power dissipation in sense resistors.
Select 5% lower value of R
SENSE
to compensate for any
parasitics associated with the PC board. Also, select a
non-inductive resistor with the appropriate wattage rating.
Compensation
The main control loop consists of an inner current loop
and an outer voltage loop. The MAX5038/MAX5041 use
an average current-mode control scheme to regulate
the output voltage (Figures 3a and 3b). I
PHASE1
and
I
PHASE2
are the inner average current loops. The VEA
output provides the controlling voltage for these current
sources. The inner current loop absorbs the inductor
pole reducing the order of the outer voltage loop to that
of a single-pole system.
A resistive feedback around the VEA provides the best
possible response, since there are no capacitors to
charge and discharge during large-signal excursions, R
F
and R
IN
determine the VEA gain. Use the following equa-
tion to calculate the value for R
F
:
where G
C
is the current-loop gain and N is number of
phases.
When designing the current-control loop ensure that the
inductor downslope (when it becomes an upslope at the
CEA output) does not exceed the ramp slope. This is a
necessary condition to avoid sub-harmonic oscillations
similar to those in peak current-mode control with insuffi-
cient slope compensation. Use the following equation to
calculate the resistor R
CF
:
For example, the maximum R
CF
is 12k
for R
SENSE
=
1.35m
.
C
CF
provides a low-frequency pole while R
CF
provides a
midband zero. Place a zero at f
Z
to obtain a phase bump
at the crossover frequency. Place a high-frequency pole
(f
P
) at least a decade away from the crossover frequency
to achieve maximum phase margin.
R
f
L
V
R
CF
SW
OUT
SENSE
≤
×
× ×
×
2
10
2
G
R
C
S
=
0 05
.
R
I
R
N G
V
F
OUT
IN
C
OUT
=
×
×
PD
R
R
SENSE
=
2 5 10
3
.
R
I
N
SENSE
OUT
=
0 045
.
C
I
t
V
OUT
STEP
RESPONSE
Q
=
×
ESR
V
I
OUT
ESR
STEP
=
(23)
(24)
(25)
(26)
(27)
(28)
(29)