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參數(shù)資料
| 型號： | MAX500BMLP |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | DAC |
| 英文描述： | CMOS, Quad, Serial-Interface 8-Bit DAC |
| 中文描述： | SERIAL INPUT LOADING, 2.5 us SETTLING TIME, 8-BIT DAC, QCC20 |
| 封裝： | LCC-20 |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 127K |
| 代理商： | MAX500BMLP |
Using an AC Referenc e
In applications where V
REF
has AC signal components,
the MAX500 has multiplying capability within the limits
of the V
REF
input range specifications. Figure 11 shows
a technique for applying a sine-wave signal to the refer-
ence input, where the AC signal is biased up before
being applied to V
REF
. Output distortion is typically less
than 0.1% with input frequencies up to 50kHz, and the
typical -3dB frequency is 700kHz. Note that V
REF
must
never be more negative than AGND.
Generating V
S S
The performance of the MAX500 is specified for both
dual and single-supply (V
SS
= 0V) operation. When the
improved performance of dual-supply operation is
desired, but only a single supply is available, a -5V V
SS
supply can be generated using an ICL7660 in one of
the circuits of Figure 12.
Digital Interfac e Applic ations
Figures 13 through 16 show examples of interfacing the
MAX500 to most popular microprocessors.
M
CMOS , Quad, S erial-Interfac e
8-Bit DAC
______________________________________________________________________________________
11
DAC B
MAX500
DGND
4
V
REF
A/B
14
1V
OUT
B
V
SS
V
DD
3
6
-5V (OR GND)
DIGITAL INPUTS NOT SHOWN
AGND
V
OUT
B
+4V
-4V
AC
REFERENCE
INPUT
+15V
15k
10k
5
ICL7660
CAP+
CAP-
V+
GND
V
OUT
IC
CAP+
CAP-
V+
GND
V
OUT
6V
ZENER
12V to 15V
10k
2N2222
10k
10
μ
F
8
3
2
10
μ
F
4
5
-5V
V
SS
OUT
10
μ
F
+5V
LOGIC
SUPPLY
-5V
V
SS
OUT
10
μ
F
8
3
4
5
10
μ
F
2
SCL
SDA
LDAC
LOAD*
80C51
P1.0
P1.1
P1.2
P1.3
CONNECT LOAD TOP1.3 FOR 3-WIRE MODE OR
CONNECT LOAD TOV
DD
FOR 2-WIRE MODE
. . . . . . .
SRO
V
OUT
A
V
OUT
B
V
OUT
C
V
OUT
D
V
REF
A/B
V
REF
C
V
REF
D
MAX500
*
ADDRESS BUS
ENACODE
B/A
C/D
CE
RD
DATA BUS
CONNECT LOAD TOP1.3 FOR 3-WIRE MODE OR
CONNECT LOAD TOV
DD
FOR 2-WIRE MODE
INT
D7
D0
Z8420
B0
B1
B2
B3
A15
A0
Z80
I/OREQ
WR
INT
D7
D0
A1
A0
SCL
SDA
LDAC
LOAD*
. .
MAX500
*
Figure 11. AC Reference Input Circuit
Figure 12. Generating -5V for V
SS
Figure 14. Z-80 with Z8420 PIO Interface
Figure 13. 80C51 Interface
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