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參數(shù)資料
| 型號(hào)： | MAX4960EUB+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 17/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CTLR HI VOLTAGE OVP 10-MSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 過壓保護(hù)控制器 |
| 應(yīng)用： | PC，PDA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-µMAX |
| 包裝： | 帶卷 (TR) |
Applications Information
MOSFET Configuration and Selection
The MAX4959/MAX4960 are used with a single MOS-
FET configuration as shown in the
Typical Operating
Circuits to regulate voltage as a low-cost solution.
The MAX4959/MAX4960 are designed with pFETs. For
lower on-resistance, the external MOSFET can be multi-
ple pFETs in parallel. In most situations, MOSFETs with
RDS(ON) specified for a VGS of 4.5V work well. Also,
MOSFETs (with VDS ≥ 30V) withstand the full +28V IN
range of the MAX4959/MAX4960.
Resistor Selection for
Overvoltage/Undervoltage Window
The MAX4959/MAX4960 include undervoltage and
overvoltage comparators for window detection (see
Figure 4). GATE1 is enhanced and after the debounce
time, the pFET is turned on when the monitored voltage
is within the selected window.
The resistor values R1, R2, and R3 can be calculated
as follows:
where RTOTAL = R1 + R2 + R3.
Use the following steps to determine the values for R1,
R2, and R3:
1) Choose a value for RTOTAL, the sum of R1, R2, and
R3. Because the MAX4959/MAX4960 have very
high input impedance, RTOTAL can be up to 5MΩ.
2) Calculate R3 based on RTOTAL and the desired
VOVLO trip point:
3) Calculate R2 based on RTOTAL, R3, and the desired
VUVLO trip point:
4) Calculate R1 based on RTOTAL, R2, and R3:
R1 = RTOTAL – R2 – R3
Note that the ratio between the externally set OVLO and
UVLO threshold must not exceed:
4 [VOVLO / VUVLO]MAX ≤ 4
VDD Capacitor Selection
VDD is regulated to +5V by a linear regulator. Since the
minimum external adjustable UVLO trip threshold is
+5V, the VDD range is +5V to +28V and the value at
VDD is:
VDD = VIN – 0.8V
where VIN = 5V to 5.8V
VDD = +5V
where VIN > 5.8V
The capacitor at VDD must be large enough to provide
power to the device for an external settable time,
tHOLD, when VIN drops to 0V. The capacitor value to
have a minimum time of tHOLD is:
C = (IVDD x tHOLD) / (VDD - VDDUVLO)
The worst case scenario is where VIN = +5V, VDD = VIN
- 0.8V = +4.2V, IVDD = 10A (max). For a tHOLD time of
20ms, C = (10A x 20ms) / (4.2V - 2.2V) = 100nF.
Note: The capacitor must be greater than 100nF for the
internal regulator to be stable, and needs to have low
ESR and low leakage current, for example, a ceramic
capacitor.
IN Bypass Considerations
For most applications, bypass IN to GND with a 1F
ceramic capacitor. If the power source has significant
inductance due to long lead length, take care to pre-
vent overshoots due to the LC tank circuit, and provide
protection if necessary to prevent exceeding the +30V
absolute maximum rating on VIN.
The MAX4959/MAX4960 provide protection against volt-
age faults up to+28V, but this does not include negative
voltages. If negative voltages are a concern, connect a
Schottky diode from IN to GND to clamp negative input
voltages.
ESD Test Conditions
The MAX4959/MAX4960 are protected from ±15kV
Human Body Model ESD on IN when IN is bypassed to
ground with a 1F ceramic capacitor.
Human Body Model
Figure 2 shows the Human Body Model and Figure 3
shows the current waveform it generates when dis-
charged into a low impedance. This model consists of a
100pF capacitor charged to the ESD voltage of interest
that is then discharged into the device through a 1.5kΩ
resistor.
R
UR
REF
TOTAL
UVLO
23
=
×
V
R
OR
REF
TOTAL
OVLO
3
=
×
V
VU
R
VO
R
UVLO
REF
TOTAL
OVLO
REF
TOTAL
=
()
+
=
()
V
R
V
R
23
3
MAX4959/MAX4960
High-Voltage OVP with Battery Switchover
_______________________________________________________________________________________
9
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