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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | MAX4959EUB+ |
| 寤犲晢锛� | Maxim Integrated Products |
| 鏂囦欢闋佹暩(sh霉)锛� | 11/17闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC CTLR HI VOLTAGE OVP 10-MSOP |
| 鐢㈠搧鍩硅〒妯″锛� | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 妯欐簴鍖呰锛� | 50 |
| 椤炲瀷锛� | 閬庡淇濊鎺у埗鍣� |
| 鎳夌敤锛� | PC锛孭DA |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 10-TFSOP锛�10-MSOP锛�0.118"锛�3.00mm 瀵級 |
| 渚涙噳鍟嗚ō鍌欏皝瑁濓細 | 10-µMAX |
| 鍖呰锛� | 绠′欢 |
MAX4959/MAX4960
ELECTRICAL CHARACTERISTICS (continued)
(VIN = +19V, TA = -40掳C to +85掳C, unless otherwise noted, CVDD = 100nF. Typical values are at TA = +25掳C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
GATE1 Leakage Current
G1ILKG
VOVS > OVREF, VUVS < UVREF, or VCB = +5V
-1
+1
A
GATE2 Leakage Current
G2ILKG
VCB = 0V
-1
+1
A
CB
Logic-Level High
VIH
1.5
V
Logic-Level Low
VIL
0.4
V
CB Pulldown Resistor
RCBPD
123
M
惟
TIMING
Debounce Time
tDEB
VOVP > VIN > VUVP for greater than tDEB for
GATE1 to go low
10
25
40
ms
GATE1 Assertion Delay from
CB Pin
t1GATE
CB = +3V to 0
rise time = fall time = 5ns (Note 3)
50
ns
GATE2 Assertion Delay from
CB Pin
t2GATE
CB = 0 to +3V
rise time = fall time = 5ns (Note 3)
50
ns
Blanking Time
tBLANK
10
25
40
ms
MAX4960
SOURCE1/GATE1 Resistance
RSG
(MAX4960)
140
200
260
k
惟
GATE1/Ground Resistance
RGG
GATE1 Asserted (MAX4960)
140
200
260
k
惟
Note 1: Operation is tested at TA= +25掳C and guaranteed by design for DFN package. Operation over specified temperature range
is tested for MAX package.
Note 2: Do not exceed absolute maximum rating; the ratio between the externally set OVLO and UVLO threshold must not exceed 4,
[OVLO/UVLO]MAX 鈮� 4.
Note 3: Assertion delay starts from switching of CB pin to reaching of 80% of GATE1/GATE2 transition. This delay is measured without
external capacitive load.
High-Voltage OVP with Battery Switchover
_______________________________________________________________________________________
3
POWER-UP RESPONSE
(RPULLUP = 1k
惟)
MAX4959/60
toc01
TIME (
渭s)
VOLTAGE
(V)
100
50
0
-50
-100
0
2
4
6
8
10
12
-2
-150
150
VIN
VDD
VGATE1
OVERVOLTAGE RESPONSE
(RPULLUP = 5k
惟)
MAX4959/60
toc02
TIME (
渭s)
VOLTAGE
(V)
100
50
0
-50
-100
5
10
15
20
25
30
0
-150
150
VIN
VDD
VGATE1
UNDERVOLTAGE RESPONSE
(WITHIN BLANKING TIME)
(RPULLUP = 1k
惟)
MAX4959/60
toc03
TIME (
渭s)
VOLTAGE
(V)
60
50
10
20
30
40
2
4
6
8
10
12
14
16
0
070
DRAIN OF P1
VIN
VGATE1
Typical Operating Characteristics
(VOVLO = 22.2V and VUVLO = 10.1V, R1 = 887k惟, R2 = 66.5k惟, R3 = 54.9k惟, all resistors 1%, OVREF = UVREF = 1.228V.)
鐩搁棞PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| MAX4949ELA+T | IC CTLR OVP W/FET 8.90V 8-UDFN |
| MAX4960EUB+T | IC CTLR HI VOLTAGE OVP 10-MSOP |
| MAX4959EUB+T | IC CTLR HI VOLTAGE OVP 10-MSOP |
| MAX4960ELB+T | IC CTLR HI VOLTAGE OVP 10-UDFN |
| MAX4944BELA+T | IC CTLR OVP W/FET 6.35V 8-UDFN |
鐩搁棞浠ｇ悊鍟�/鎶€琛撳弮鏁�(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| MAX4959EUB+ | 鍔熻兘鎻忚堪:闆绘祦鍜岄浕鍔涚洠(ji膩n)鎺у櫒銆佽绡€(ji茅)鍣� OVP w/Battery Switchover RoHS:鍚� 鍒堕€犲晢:STMicroelectronics 鐢㈠搧:Current Regulators 闆绘簮闆诲-鏈€澶�:48 V 闆绘簮闆诲-鏈€灏�:5.5 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 150 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:HPSO-8 灏佽:Reel |
| MAX4959EUB+T | 鍔熻兘鎻忚堪:闆绘祦鍜岄浕鍔涚洠(ji膩n)鎺у櫒銆佽绡€(ji茅)鍣� OVP w/Battery Switchover RoHS:鍚� 鍒堕€犲晢:STMicroelectronics 鐢㈠搧:Current Regulators 闆绘簮闆诲-鏈€澶�:48 V 闆绘簮闆诲-鏈€灏�:5.5 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 150 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:HPSO-8 灏佽:Reel |
| MAX495C/D | 鍔熻兘鎻忚堪:閬嬬畻鏀惧ぇ鍣� - 閬嬫斁 Single Micropower Single-Supply Rail-to-Rail Op Amp RoHS:鍚� 鍒堕€犲晢:STMicroelectronics 閫氶亾鏁�(sh霉)閲�:4 鍏辨ā鎶戝埗姣旓紙鏈€灏忓€硷級:63 dB 杓稿叆瑁滃劅闆诲:1 mV 杓稿叆鍋忔祦锛堟渶澶у€硷級:10 pA 宸ヤ綔闆绘簮闆诲:2.7 V to 5.5 V 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:QFN-16 杞夋彌閫熷害:0.89 V/us 闂滈枆:No 杓稿嚭闆绘祦:55 mA 鏈€澶у伐浣滄韩搴�:+ 125 C 灏佽:Reel |
| MAX495C/D DIE | 鍒堕€犲晢:Maxim Integrated Products 鍔熻兘鎻忚堪: |
| MAX495CPA | 鍔熻兘鎻忚堪:閬嬬畻鏀惧ぇ鍣� - 閬嬫斁 Single uPower Single Supply Rail-Rail RoHS:鍚� 鍒堕€犲晢:STMicroelectronics 閫氶亾鏁�(sh霉)閲�:4 鍏辨ā鎶戝埗姣旓紙鏈€灏忓€硷級:63 dB 杓稿叆瑁滃劅闆诲:1 mV 杓稿叆鍋忔祦锛堟渶澶у€硷級:10 pA 宸ヤ綔闆绘簮闆诲:2.7 V to 5.5 V 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:QFN-16 杞夋彌閫熷害:0.89 V/us 闂滈枆:No 杓稿嚭闆绘祦:55 mA 鏈€澶у伐浣滄韩搴�:+ 125 C 灏佽:Reel |
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