參數(shù)資料
型號: MAX4950CTO+T
廠商: Maxim Integrated Products
文件頁數(shù): 4/5頁
文件大?。?/td> 0K
描述: IC PCIE REDRIVER 3.3V 42TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: 均衡器,轉(zhuǎn)接驅(qū)動器
電源電壓: 3.3V
安裝類型: 表面貼裝
封裝/外殼: 42-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 42-TQFN-EP(3.5x9)
包裝: 帶卷 (TR)
V. Quality Assurance Information
A. Quality Assurance Contacts:
Ken Wendel (Director, Reliability Engineering)
Bryan Preeshl (Managing Director of QA)
B. Outgoing Inspection Level:
0.1% for all electrical parameters guaranteed by the Datasheet.
0.1% For all Visual Defects.
C. Observed Outgoing Defect Rate:
< 50 ppm
D. Sampling Plan:
Mil-Std-105D
VI. Reliability Evaluation
A. Accelerated Life Test
MAX4950CTO+
The results of the 135°C biased (static) life test are shown in Table 1. Using these results, the Failure Rate ( ) is calculated as
follows:
=
1
=
1.83
(Chi square value for MTTF upper limit)
MTTF
192 x 4340 x 48 x 2
(where 4340 = Temperature Acceleration factor assuming an activation energy of 0.8eV)
= 22.4 x 10
-9
= 22.4 F.I.T. (60% confidence level @ 25°C)
The following failure rate represents data collected from Maxim’s reliability monitor program. Maxim performs quarterly
1000 hour life test monitors on its processes. This data is published in the Product Reliability Report found at http://www.maxim-
ic.com/. Current monitor data for the G4 Process results in a FIT Rate of 0.2 @ 25C and 3.6 @ 55C (0.8 eV, 60% UCL)
B. Moisture Resistance Tests
The industry standard 85°C/85%RH or HAST testing is monitored per device process once a quarter.
C. E.S.D. and Latch-Up Testing
The AJ42 die type has been found to have all pins able to withstand a HBM transient pulse of +/-2500 V per
JEDEC JESD22-A114. Latch-Up testing has shown that this device withstands a current of +/-250 mA, 1.5x VCCMax
Overvoltage per JESD78.
Maxim Integrated Products. All rights reserved.
Page 4/5
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