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參數(shù)資料
| 型號： | MAX494MJD |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | High-Output RS-485 Transceiver 8-SOIC -40 to 85 |
| 中文描述： | QUAD OP-AMP, 1200 uV OFFSET-MAX, 0.5 MHz BAND WIDTH, CDIP14 |
| 封裝： | CERDIP-14 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大小： | 230K |
| 代理商： | MAX494MJD |
M
Because the MAX492/MAX494/MAX495 have excellent
stability, no isolation resistor is required, except in the
most demanding applications. This is beneficial
because an isolation resistor would degrade the low-
frequency performance of the circuit.
Power-Up S ettling T ime
The MAX492/MAX494/MAX495 have a typical supply
current of 150μA per op amp. Although supply current is
already low, it is sometimes desirable to reduce it further
by powering down the op amp and associated ICs for
periods of time. For example, when using a MAX494 to
buffer the inputs to a multi-channel analog-to-digital con-
verter (ADC), much of the circuitry could be powered
down between data samples to increase battery life. If
samples are taken infrequently, the op amps, along with
the ADC, may be powered down most of the time.
When power is reapplied to the MAX492/MAX494/
MAX495, it takes some time for the voltages on the sup-
ply pin and the output pin of the op amp to settle.
Supply settling time depends on the supply voltage, the
value of the bypass capacitor, the output impedance of
the incoming supply, and any lead resistance or induc-
tance between components. Op amp settling time
depends primarily on the output voltage and is slew-rate
limited. With the noninverting input to a voltage follower
held at mid-supply (Figure 10), when the supply steps
from 0V to V
CC
, the output settles in approximately 4μs
for V
CC
= +3V (Figure 11a) or 10μs for V
CC
= +5V
(Figure 11b).
Power S upplies and Layout
The MAX492/MAX494/MAX495 operate from a single
2.7V to 6V power supply, or from dual supplies of
±1.35V to ±3V. For single-supply operation, bypass the
power supply with a 1μF capacitor in parallel with a
0.1μF ceramic capacitor. If operating from dual sup-
plies, bypass each supply to ground.
Good layout improves performance by decreasing the
amount of stray capacitance at the op amp’s inputs and
output. To decrease stray capacitance, minimize both
trace lengths and resistor leads and place external
components close to the op amp’s pins.
Rail-to-Rail Buffers
The Typical Operating Circuitshows a MAX495 gain-of-
two buffer driving the analog input to a MAX187 12-bit
ADC. Both devices run from a single 5V supply, and the
converter’s internal reference is 4.096V. The MAX495’s
typical input offset voltage is 200μV. This results in an
error at the ADC input of 400μV, or less than half of one
least significant bit (LSB). Without offset trimming, the
op amp contributes negligible error to the conversion
result.
S ingle/Dual/Quad, Mic ropower,
S ingle-S upply Rail-to-Rail Op Amps
14
______________________________________________________________________________________
V
CC
1V/div
V
OUT
500mV/div
5
μ
s/div
V
CC
2V/div
V
OUT
1V/div
5
μ
s/div
Figure 11b. Power-Up Settling Time (V
CC
= +5V)
Figure 11a. Power-Up Settling Time (V
CC
= +3V)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX495 | High-Output RS-485 Transceiver 8-SOIC -40 to 85 |
| MAX495CPA | High-Output RS-485 Transceiver 8-PDIP -40 to 85 |
| MAX495CSA | High-Output RS-485 Transceiver 8-PDIP -40 to 85 |
| MAX495EPA | High-Output RS-485 Transceiver 8-SOIC -40 to 85 |
| MAX495ESA | High-Output RS-485 Transceiver 8-SOIC -40 to 85 |
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