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參數(shù)資料
| 型號(hào)： | MAX4928BETN+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 6/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DISPLAY-PORT/PCIE SW 56-TQFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | PCI Express®(PCIe), DisplayPort™ |
| 類型： | 無源開關(guān) |
| 應(yīng)用： | 臺(tái)式，筆記本電腦 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 56-TQFN-EP（5x11） |
| 包裝： | 帶卷 (TR) |
MAX4928A/MAX4928B
DisplayPort/PCIe Passive Switches
2
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS
(VDD = +3.3V ±10%, TA =TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +3.3V, TA = +25°C, unless otherwise
noted.) (Note 3)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG SWITCH
Analog Signal Range
IN_, X_, OUT_,
D_, TX_, HPD_,
RX_, AUX_
-0.1
(VDD -
1.8)
V
Voltage Between IN and D/TX, X
and HPD/RX1, and OUT and
AUX/RX0
|VIN_ - VTX_|,
|VIN_ - VD_|,
|VX_ - VHPD_|,
|VX_ - VRX1_|,
|VOUT_ -
VAUX_|,
|VOUT_ - VRX0_|
01.8
V
On-Resistance
RON
IIN_ = IX_ = IOUT_ = 15mA, VD_, VTX_,
VHPD_, VAUX_, or VRX_ = 0V, +1.2V
8
Ω
On-Resistance Match
Between Pairs of Same Channel
ΔRON
VDD = +3.0V, IIN_ = IX_ = IOUT_= 15mA,
VD_, VTX_, VHPD_, VAUX_, or VRX_ = 0V
(Notes 4, 5)
0.1
2
On-Resistance Match
Between Channels
ΔRON
VDD = +3.0V, IIN_ = IX_ = IOUT_= 15mA,
VD_, VTX_, VHPD_, VAUX_, or VRX_ = 0V
(Notes 4, 5)
1.5
4
Ω
On-Resistance Flatness
RFLAT(ON)
VDD = +3.0V, IIN_ = IX_ = IOUT_= 15mA,
VD_, VTX_, VHPD_, VAUX_, or VRX_ = 0V,
+1.2V (Notes 5, 6)
0.3
1.5
Ω
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND, unless otherwise noted.)
VDD ...........................................................................-0.3V to +4V
LE, SEL, IN_, X_, OUT_, D_, TX_, HPD_, RX_, AUX_
(Note 1) ...............................................-0.3V to + (VDD + 0.3V)
|VIN_ - VTX_|, |VIN_ - VD_|, |VX_ - VHPD_|, |VX_ - VRX1_|,
|VOUT_ - VAUX_|, |VOUT_ - VRX0_| (Note 1) ...................0 to +2V
Continuous Current (IN_ to D_/TX_, X_ to HPD_/RX1_,
OUT_ to AUX_/RX0_ .....................................................±70mA
Peak Current (IN_ to D_/TX_, X_ to HPD_/RX1_, OUT_ to
AUX_/RX0_) (pulsed at 1ms, 10% duty cycle) .............±70mA
Continuous Current (LE, SEL)...........................................±30mA
Peak Current (LE, SEL)
(pulsed at 1ms, 10% duty cycle)..................................±70mA
Continuous Power Dissipation (TA = +70°C) for Multilayer Board
56-Pin TQFN (derate 41.0mW/°C above +70°C) .......3279mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Package Junction-to-Ambient Thermal Resistance (
θJA)
(Note 2) .....................................................................24.4°C/W
Package Junction-to-Case Thermal Resistance (
θJC)
(Note 2) .......................................................................1.5°C/W
Lead Temperature (soldering) .........................................+300°C
Note 1: Signals on IN_, X_, OUT_, D_, TX_, HPD_, RX_, or AUX_, LE, SEL exceeding VDD or GND are clamped by internal diodes.
Limit forward-diode current to maximum current rating.
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a 4-layer
board. For detailed information on package thermal considerations, see www.maxim-ic.com/thermal-tutorial.
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