參數(shù)資料
型號: MAX4924ELT+T
廠商: Maxim Integrated Products
文件頁數(shù): 6/7頁
文件大?。?/td> 0K
描述: IC CTLR OVP W/EXT PFET 6-UDFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: 過壓保護(hù)控制器
應(yīng)用: 手機(jī),數(shù)碼相機(jī),媒體播放器
安裝類型: 表面貼裝
封裝/外殼: 6-WFDFN
供應(yīng)商設(shè)備封裝: 6-uDFN(1.5x1.0)
包裝: 帶卷 (TR)
MAX4923–MAX4926
IN Bypass Consideration
For most applications, bypass IN to GND with a 1F
ceramic capacitor. If the power source has significant
inductance due to long lead length, take care to pre-
vent overshoots due to the LC tank circuit and provide
protection if necessary to prevent exceeding the 30V
absolute maximum rating on IN.
ESD Test Conditions
The MAX4923–MAX4926 are ESD protected to ±15kV
(typ) Human Body Model on IN when IN is bypassed to
ground with a 1F ceramic capacitor as close as possi-
ble to IN.
Human Body Model
Figure 4 shows the Human Body Model and Figure 5
shows the current waveform it generates when dis-
charged into a low impedance. This model consists of
a 100pF capacitor charged to the ESD voltage of inter-
est that is then discharged into the device through a
1.5k
Ω resistor.
Overvoltage Protectors with
External pFET
6
_______________________________________________________________________________________
PART
CONFIGURATON/
PACKAGE
VDS MAX
(V)
RON MAX (m
Ω)
at VGS = -4.5V
MANUFACTURER
Si3993DV
Dual/TSOP-6
-30
245 each
Si1433DH
Single/SOT-363
-30
260
Si3983DV
Dual/TSOP-6
-20
110 each
Si1413DH
Single/SOT-363
-20
115
Si5933DC
Dual/1206-8
-20
110 each
Si6991DQ
Dual/TSSOP-8
-30
68 each
Vishay Siliconix
www.vishay.com
Table 1. MOSFETS Suggestions
CHARGE-CURRENT
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
100pF
RC
1M
Ω
RD
1.5k
Ω
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
Figure 4. Human Body ESD Test Model
IP 100%
90%
36.8%
tRL
TIME
tDL
CURRENT WAVEFORM
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
Ir
10%
0
AMPERES
Figure 5. Human Body Model Current Waveform
Chip Information
PROCESS: BiCMOS
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