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參數(shù)資料
| 型號： | MAX4867ELT+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 10/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CTLR OVP REVERSE POL 6UDFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 技術(shù)： | 混合技術(shù) |
| 電路數(shù)： | 1 |
| 應(yīng)用： | 通用 |
| 封裝/外殼： | 6-WDFN |
| 供應(yīng)商設(shè)備封裝： | 6-uDFN（2x2） |
| 包裝： | 帶卷 (TR) |
MAX4864L/MAX4865L/MAX4866L/MAX4867
Overvoltage Protection Controllers
with Reverse Polarity Protection
8
_______________________________________________________________________________________
Applications Information
MOSFET Configuration
The MAX4864L/MAX4865L/MAX4866L/MAX4867 can be
used with either a complementary MOSFET configuration
as shown in the
Typical Operating Circuit, or can be con-
figured with a single p-channel MOSFET and back-to-
back n-channel MOSFETs as shown in Figure 6.
The MAX4864L/MAX4865L/MAX4866L/MAX4867 can drive
either a complementary MOSFET or a single p-channel
MOSFET and back-to-back n-channel MOSFETs. The
back-to-back configuration has almost zero reverse cur-
rent when the adapter is not present or when the
adapter voltage is below the UVLO threshold.
If reverse current leakage is not a concern, a single
MOSFET can be used. This approach has half the loss
of the back-to-back configuration when used with simi-
lar MOSFET types and is a lower cost solution. Note
that if the input is actually pulled low, the output will
also be pulled low due to the parasitic body diode in
the MOSFET. If this is a concern, then the back-to-back
configuration should be used.
MOSFET Selection
The MAX4864L/MAX4865L/MAX4866L/MAX4867 are
designed for use with a complementary MOSFET or sin-
gle p-channel and dual back-to-back n-channel
MOSFETs. In most situations, MOSFETs with RON spec-
ified for a VGS of 4.5V work well. Also the VDS should
be +30V for the MOSFET to withstand the full +28V IN
range of the MAX4864L/MAX4865L/MAX4866L/
MAX4867. Table 1 shows a selection of MOSFETs
which are appropriate for use with the MAX4864L/
MAX4865L/MAX4866L/MAX4867.
IN Bypass Considerations
For most applications, bypass ADAPTER to GND with a
1F ceramic capacitor. If the power source has signifi-
cant inductance due to long lead length, take care to
prevent overshoots due to the LC tank circuit and pro-
vide protection if necessary to prevent exceeding the
+30V absolute maximum rating on IN.
ESD Test Conditions
ESD performance depends on a number of conditions. The
MAX4864L/MAX4865L/MAX4866L/MAX4867 are specified
for ±15kV typical ESD resistance on IN when ADAPTER is
bypassed to ground with a 1F ceramic capacitor.
Human Body Model
Figure 7 shows the Human Body Model, and Figure 8
shows the current waveform it generates when dis-
charged into a low impedance. This model consists of a
100pF capacitor charged to the ESD voltage of interest,
which is then discharged into the device through a
1.5k
Ω resistor.
P
NN
ADAPTER
-28V TO +28V
OUTPUT
VIO
IN
FLAG
GATEN
1
μF
GND
GATEP
MAX4864L
MAX4865L
MAX4866L
MAX4867
Figure 6. Back-to-Back External MOSFET Configuration
Table 1. MOSFET Suggestions
PART
CONFIGURATION/
PACKAGE
VGS MAX
(V)
VDS MAX
(V)
RON AT 4.5V (m
Ω)
MANUFACTURER
+30
143 (n-MOSFET)
Si5504DC
Complementary
MOSFET/1206-8
±20
-30
290 (p-MOSFET)
Si5902DC
Dual/1206-8
±20
+30
143 (n-MOSFET)
Si1426DH
Single/DFN-6
±20
+30
115 (n-MOSFET)
Si5435DC
Single/1206-8
±20
-30
80 (p-MOSFET)
Vishay Siliconix
FDC6561AN
Dual/SSOT-6
±20
+30
145 (n-MOSFET)
FDG315N
Single/DFN-6
±20
+30
160 (n-MOSFET)
FDC658P
Single/SSOT-6
±20
-30
75 (p-MOSFET)
FDC654P
Single/SSOT-6
±20
-30
125 (p-MOSFET)
Fairchild Semiconductor
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