參數(shù)資料
型號: MAX4719EUB
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 運(yùn)動控制電子
英文描述: 300MHz Bandwidth, Dual SPDT Analog Switch in UCSP
中文描述: DUAL 1-CHANNEL, SGL POLE DOUBLE THROW SWITCH, PDSO10
封裝: MICRO MAX PACKAGE-10
文件頁數(shù): 8/11頁
文件大小: 282K
代理商: MAX4719EUB
Test Circuits/Timing Diagrams
tr < 5ns
tf < 5ns
50%
V
IL
LOGIC
INPUT
R
L
300
COM_
GND
IN_
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
OUT
= V
N_
(
R
L
)
V
L
+ R
ON
V
N_
V
IH
t
OFF
0V
NO_
OR NC_
0.9 x V
0UT
0.9 x V
OUT
t
ON
V
OUT
SWITCH
OUTPUT
LOGIC
INPUT
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
V+
C
35pF
V+
V
OUT
MAX4719
Figure 1. Switching Time
50%
V
IH
V
IL
LOGIC
INPUT
V
OUT
0.9 x V
OUT
t
BBM
LOGIC
INPUT
R
L
300
GND
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
NO_
IN_
NC_
V
OUT
V+
V+
C
35pF
V
N_
COM_
MAX4719
Figure 2. Break-Before-Make Interval
M
Power-Supply Sequencing and
Overvoltage Protection
Caution: Do not exceed the absolute maximum rat-
ings because stresses beyond the listed ratings
may cause permanent damage to the device.
Proper power-supply sequencing is recommended for
all CMOS devices. Always apply V+ before applying
analog signals, especially if the analog signal is not
current-limited.
UCSP Package Considerations
For general UCSP package information and PC layout
considerations, please refer to the Maxim Application
Note (Wafer-Level Chip-Scale Package).
UCSP Reliability
The chip-scale package (UCSP) represents a unique
packaging form factor that may not perform equally to a
packaged product through traditional mechanical relia-
bility tests. UCSP reliability is integrally linked to the
user
s assembly methods, circuit board material, and
usage environment. The user should closely review
these areas when considering use of a UCSP package.
Performance through Operating Life Test and Moisture
Resistance remains uncompromised as it is primarily
determined by the wafer-fabrication process.
Mechanical stress performance is a greater considera-
tion for a UCSP package. UCSPs are attached through
direct solder contact to the user
s PC board, foregoing
the inherent stress relief of a packaged product lead
frame. Solder joint contact integrity must be consid-
ered. Information on Maxim
s qualification plan, test
data, and recommendations are detailed in the UCSP
application note, which can be found on Maxim
s web-
site at www.maxim-ic.com.
Chip Information
TRANSISTOR COUNT: 235
PROCESS: BiCMOS
20
, 300MHz Bandwidth, Dual SPDT Analog
Switch in UCSP
8
_______________________________________________________________________________________
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