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參數(shù)資料
| 型號： | MAX4473EUA |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Low-Cost, Low-Voltage, PA Power Control Amplifier for GSM Applications in 8-Pin レMAX |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO8 |
| 封裝： | MICRO MAX PACKAGE-8 |
| 文件頁數(shù)： | 4/6頁 |
| 文件大?。?/td> | 140K |
| 代理商： | MAX4473EUA |
Detailed Desc ription
The MAX4473 is a voltage-controlled, unidirectional,
high-side current setting amplifier for applications
where accurate control of PA supply current is desired.
This device is intended for wireless TDMA based sys-
tems (GSM, DECT), where tight restrictions over the
PA’s transmit burst and output power require closed-
loop control over the PA’s output power. When used
with a PA, the MAX4473 functions as a voltage-con-
trolled constant current source, accurately setting PA
supply current by varying the gain of the PA. If you
know the output power versus supply current profile for
the PA, you can set the PA’s output power by control-
ling the amount of supply current delivered to the PA.
The MAX4473 is composed of an input buffer (A1), a
voltage-to-current converting amplifier (A2), and a rail-
to-rail output error amplifier (A3) (see Typical Operating
Circuit. External gain and sense resistors allow pro-
grammability for a wide range of applications.
In the Typical Operating Circuit PA supply current
flows from the system supply, through the external cur-
rent sense resistor (R
SENSE
), to the PA. The rail-to-rail
outputs of the error amplifier, A3, adjust the gain of the
PA until the voltage drop across R
SENSE
equals the
voltage drop across external gain resistor, RG1. The
voltage drop across RG1 sets the voltage drop across
R
SENSE
, with a larger voltage drop resulting in more
current delivered to the PA. The voltage drop across
RG1 is set by A1, A2, and the V-to-I FET, Q1. A voltage
applied to the PC input of the input buffer is divided by
four by a resistor-divider network. A2 forces its inverting
input and the source of Q1 to V
PC
/ 4, thus setting a
voltage across RG3. The resulting current through RG3
sets the current through RG1. This unique architecture
allows the supply current to be set independent of sup-
ply voltage. Set PA supply current according to the fol-
lowing equation:
I
CCPA
= ( V
PC
·
RG1 ) / ( 4
·
R
SENSE
·
RG3 )
S hutdown Mode
When
SHDN
is a logic-level low (
SHDN
< 0.4V), ampli-
fiers A1, A2, and A3 are off, Q1 is turned off, and the
output of A3 is actively pulled to ground with an N-
channel FET. Supply current is reduced to less than
1μA in shutdown mode. Typical power-up time is 0.9μs
and typical power-down time is 0.3μs, using the
MAX4473 test circuit.
Applic ations Information
Gain Resistor S elec tion
(RG1, RG2, RG3)
For proper operation, do not make the value of external
gain resistors RG1 and RG2 larger than twice the value
of RG3. In most practical applications, choose RG1
smaller than RG3 to limit the voltage drop over RG1
and R
SENSE
. A large voltage drop over R
SENSE
sub-
stantially reduces the voltage applied to the PA, thus
reducing PA output power. Set RG2 equal to RG1 to
compensate for the input bias currents of A3.
Recommended values for RG3 are between 1k
and
10k
.
M
Low-Cost, Low-Voltage, PA Power Control
Amplifier for GS M Applic ations in 8-Pin μMAX
4
_______________________________________________________________________________________
NAME
FUNCTION
1
SR1
Inverting Input of Error Amplifier and Drain of V-to-I FET, Q1. Connect to supply side of current-sense resis-
tor, R
SENSE
, through gain resistor RG1.
Noninverting Input of Error Amplifier. Connect to load side of current-sense resistor, R
SENSE
, through gain
resistor RG2. Set RG2 equal to RG1.
2
SR2
PIN
3
SHDN
Shutdown Input. Drive
SHDN
low to disable all amplifiers, pull OUT to GND, set the gate-to-source voltage
of the V-to-I FET (Q1) to 0, and reduce supply current to less than 1μA. Drive high or connect to V
CC
for nor-
mal operation.
Power Control Input. Apply a voltage to PC to set a DC current through the sense resistor to control PA bias.
Ground
4
5
PC
GND
8
V
CC
+2.7V to +6.5V Voltage Supply Input. Bypass to ground with a 0.1μF capacitor.
7
OUT
Output of Error Amplifier. Connect to gain control pin of power amplifier in bias control applications.
6
SR3
Inverting Input of V-to-I Converter and Source of V-to-I FET, Q1. Connect to ground through gain resistor
RG3.
Pin Desc ription
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