參數(shù)資料
型號： MAX4358ECE+TD
廠商： Maxim Integrated Products
文件頁數(shù)： 25/43頁
文件大小： 0K
描述： IC VIDEO CROSSPOINT SWIT 144TQFP
產(chǎn)品變化通告： Product Discontinuation 28/Nov/2011
標準包裝： 250
功能： 視頻交叉點開關
電路： 1 x 32:16
電壓電源： 單/雙電源
電壓 - 電源，單路/雙路(±)： 5V，± 3 V ~ 5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 144-TQFP
供應商設備封裝： 144-TQFP（20x20）
包裝： 帶卷 (TR)
MAX4358
32 x 16 Nonblocking Video Crosspoint Switch
with On-Screen Display Insertion and I/O Buffers
______________________________________________________________________________________
31
SCLK is the serial-data clock which clocks data into the
data input registers (Figure 3). Data at DIN is loaded in
at each falling edge of SCLK. DOUT is the data shifted
out of the 112-bit Complete Matrix Mode register (Mode
= 1). DIN passes directly to DOUT when in Individual
Output Address Mode (Mode = 0).
The falling edge of
UPDATE latches the data and pro-
grams the matrix. When using Individual Output
Address Mode, the address recognition output
AOUT
drives low when control-word bits D14 to D11 match
the address programming inputs (A3–A0) and
UPDATE
is low (Table 1). Table 1 is the operation truth table.
Programming the Matrix
The MAX4358 offers two programming modes:
Individual Output Address Mode and Complete Matrix
Mode. These two distinct programming modes are
selected by toggling a single MODE pin high or low.
Both modes operate with the same physical board lay-
out. This flexibility allows initial programming of the IC
by daisy-chaining and sending one long data word
while still being able to immediately address and
update individual outputs in the matrix.
Individual Output Address Mode (MODE = 0)
Drive MODE to logic low to select Mode 0. Individual
outputs are programmed via the serial interface with a
single 16-bit control word. The control word consists of
a don’t care MSB, the chip address bits, output
address bits, an output enable/disable bit, an output
gain-set bit, and input address bits (Table 2 through
Table 6, and Figure 2).
16-BIT INDIVIDUAL OUTPUT
ADDRESS MODE REGISTER
112-BIT COMPLETE MATRIX MODE REGISTER
OUTPUT ADDRESS DECODE
MODE
DATA
ROUTING
GATE
A
B
S
MODE
SWITCH MATRIX
OUTPUT ENABLE
DOUT
SWITCH DECODE
DIN
SCLK
MODE
CE
SCLK
MODE
CE
UPDATE
EN
A0–A3
CHIP ADDRESS
AOUT
4
11
7
112
1
7
112
512
16
112-BIT PARALLEL LATCH
Figure 2. Serial Interface Block Diagram
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