參數(shù)資料
型號: MAX4356ECD
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 運動控制電子
英文描述: 16x16 Nonblocking Video Crosspoint Switch with On-Screen Display Insertion and I/O Buffers
中文描述: 16-CHANNEL, CROSS POINT SWITCH, PQFP128
封裝: 14 X 20 MM, 1.40 MM HEIGHT, TQFP-128
文件頁數(shù): 28/41頁
文件大小: 853K
代理商: MAX4356ECD
M
16 x 16 Nonbloc king Video Crosspoint S witc h
with On-S c reen Display Insertion and I/O Buffers
28
______________________________________________________________________________________
Pin Desc ription
PIN
NAME
N.C.
FUNCTION
1
4, 30
38, 103
No Connection. Not internally connected. Connect to AGND.
5, 7, 9, 11, 13,
15, 17, 19, 21, 23,
25, 27, 121, 123,
125, 127
IN0
IN15
Buffered Analog Inputs
6, 8, 10, 12, 14,
16, 18, 20, 65, 66,
100, 101, 102,
120, 122, 124,
126
AGND
Analog Ground
22, 24, 26, 28
A3
A0
Address Programming Inputs. Connect to DGND or V
DD
to select the address for individual
output address mode. See Table 3.
29, 67, 71, 75, 79,
83, 87, 91, 95, 99
V
CC
Positive Analog Supply. Bypass each pin with a 0.1
μ
F capacitor to AGND. Connect a single
10
μ
F capacitor from one V
CC
pin to AGND.
39
DOUT
Serial Data Output. In complete matrix mode, data is clocked through the 96-bit Matrix Control
Shift register. In individual output address mode, data at DIN passes directly to DOUT.
40
41
42
43
DGND
AOUT
SCLK
CE
Digital Ground
Address Recognition Output.
AOUT
drives low after successful chip address recognition.
Serial Clock Input
Clock Enable Input. Drive low to enable the serial data interface.
44
MODE
Serial Interface Mode Select Input. Drive high for complete matrix mode (mode 1), or drive low
for individual output address mode (mode 0).
45
RESET
Asynchronous Reset Input/Output. Drive
RESET
low to initiate hardware reset. All matrix
settings are set to power-up defaults and all analog outputs are disabled. Additional power-on
reset delay may be set by connecting a small capacitor from
RESET
to DGND.
46
47
48
UPDATE
DIN
V
DD
Update Input. Drive
UPDATE
low to transfer data from Mode registers to the matrix switch.
Serial Data Input. Data is clocked in on the falling edge of SCLK.
Digital Logic Supply. Bypass V
DD
with a 0.1
μ
F capacitor DGND.
49
64
OSDKEY0
OSDKEY15
Digital Control Input. Control for the fast 2:1 OSD insertion multiplexer routing signal to output
buffers. A logic high routes the programmed IN_ analog input signal to the output buffer. A
logic low routes the dedicated OSDFILL_ input to the corresponding output buffer.
68, 70, 72, 74, 76,
78, 80, 82, 84, 86,
88, 90, 92, 94, 96,
98
OUT0
OUT15
Buffered Analog Outputs. Gain is individually programmable for A
V
= +1V/V or A
V
= +2V/V
through the serial interface. Outputs may be individually disabled (high impedance). On
power-up or assertion of
RESET
, all outputs are disabled.
69, 73, 77, 81, 85,
89, 93, 97, 128
V
EE
Negative Analog Supply. Bypass each pin with a 0.1
μ
F capacitor to AGND. Connect a single
10
μ
F capacitor from one V
EE
pin to AGND.
104
119
OSDFILL0
OSDFILL15
Dedicated OSD Analog Signal Buffered Inputs. For each output buffer amplifier OSDFILL, the
input signal is routed to output buffer amplifier OUT when the corresponding OSDKEY is low.
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